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[23.128.96.18]) by mx.google.com with ESMTP id a26si6509556eds.337.2020.07.28.04.43.04; Tue, 28 Jul 2020 04:43:26 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=zX8tO8sd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729129AbgG1Lmi (ORCPT + 99 others); Tue, 28 Jul 2020 07:42:38 -0400 Received: from mail.kernel.org ([198.145.29.99]:52072 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729036AbgG1Lmh (ORCPT ); Tue, 28 Jul 2020 07:42:37 -0400 Received: from quaco.ghostprotocols.net (179.176.1.55.dynamic.adsl.gvt.net.br [179.176.1.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 11693206D4; Tue, 28 Jul 2020 11:42:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1595936557; bh=hWJ40JidbmXhL97JcpfTJY7CxeEWoXzgt7+q2CZAG/g=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=zX8tO8sdlGhRmV6aDnpqWVPi+6lz2rG8p3iC3A//htu2cYRdvKWJ8GtU2cnQIw4Ui km8TqpYwIbEnSY0fqJiH+ESQgFLDkv2RpzsIgCOSRzUFJZoGqnyEtNpFQEZKF93DOU Olb/73IPiegu8iawNLx293YjnZPA4EZdzu7uqaSk= Received: by quaco.ghostprotocols.net (Postfix, from userid 1000) id AE929404B1; Tue, 28 Jul 2020 08:42:34 -0300 (-03) Date: Tue, 28 Jul 2020 08:42:34 -0300 From: Arnaldo Carvalho de Melo To: Mathieu Poirier Cc: Wei Li , leo.yan@linaro.org, Suzuki K Poulose , Mike Leach , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Kim Phillips , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Peter Zijlstra , Ingo Molnar , guohanjun@huawei.com Subject: Re: [PATCH v2 2/2] perf tools: ARM SPE code cleanup Message-ID: <20200728114234.GA3328@kernel.org> References: <20200724071111.35593-1-liwei391@huawei.com> <20200724071111.35593-3-liwei391@huawei.com> <20200727203436.GC2381376@xps15> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200727203436.GC2381376@xps15> X-Url: http://acmel.wordpress.com Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Em Mon, Jul 27, 2020 at 02:34:36PM -0600, Mathieu Poirier escreveu: > On Fri, Jul 24, 2020 at 03:11:11PM +0800, Wei Li wrote: > > - Firstly, the function auxtrace_record__init() will be invoked only > > once, the variable "arm_spe_pmus" will not be used afterwards, thus > > we don't need to check "arm_spe_pmus" is NULL or not; > > - Another reason is, even though SPE is micro-architecture dependent, > > but so far it only supports "statistical-profiling-extension-v1" and > > we have no chance to use multiple SPE's PMU events in Perf command. > > I find the above changelog somewhat out of touch with the patch itself. The > only thing that is happening here is the removal of a useless check and a fix > for a memory leak. > > Once again whether Arnaldo wants to make the changes by hand or not you may have > to resubmit. I'll fix it now, thanks for reviewing. - Arnaldo > Reviewed-by: Mathieu Poirier > > > > > So remove the useless check code to make it clear. > > > > Signed-off-by: Wei Li > > --- > > tools/perf/arch/arm/util/auxtrace.c | 9 ++++----- > > 1 file changed, 4 insertions(+), 5 deletions(-) > > > > diff --git a/tools/perf/arch/arm/util/auxtrace.c b/tools/perf/arch/arm/util/auxtrace.c > > index 28a5d0c18b1d..b187bddbd01a 100644 > > --- a/tools/perf/arch/arm/util/auxtrace.c > > +++ b/tools/perf/arch/arm/util/auxtrace.c > > @@ -57,17 +57,15 @@ struct auxtrace_record > > struct evsel *evsel; > > bool found_etm = false; > > struct perf_pmu *found_spe = NULL; > > - static struct perf_pmu **arm_spe_pmus = NULL; > > - static int nr_spes = 0; > > + struct perf_pmu **arm_spe_pmus = NULL; > > + int nr_spes = 0; > > int i = 0; > > > > if (!evlist) > > return NULL; > > > > cs_etm_pmu = perf_pmu__find(CORESIGHT_ETM_PMU_NAME); > > - > > - if (!arm_spe_pmus) > > - arm_spe_pmus = find_all_arm_spe_pmus(&nr_spes, err); > > + arm_spe_pmus = find_all_arm_spe_pmus(&nr_spes, err); > > > > evlist__for_each_entry(evlist, evsel) { > > if (cs_etm_pmu && > > @@ -84,6 +82,7 @@ struct auxtrace_record > > } > > } > > } > > + free(arm_spe_pmus); > > > > if (found_etm && found_spe) { > > pr_err("Concurrent ARM Coresight ETM and SPE operation not currently supported\n"); > > -- > > 2.17.1 > > -- - Arnaldo