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bh=Gol3YEjZg+DdUDqVA5CTPFx2cwX3l9O5rj/E8q5KIWU=; b=sMnhvafK6/tcKtUuXjUveGzO618QcFijWfe7SUM71YZXzzMkD4fZX7RIwjmeXnRGsU N0vQuOEdaU8yxi+Id9/16Rn5UGiNqXk+CbGlrVc+GHarbM6u7vQvR5E66aFmO+v2wx/a AfrZN/ezswvoGgb8KYMWsXdvkHxaZ/Y+5Ot6BgxiR+srCFHK1GJ2+eKaKl4bZ5lxHgLS nuR6bQ7JtTFwbDb7fZ4a9HuwAXizyAWA0SNn7jEyGcl0BUuL9XGtFz9Hmo3/nbxW290o o3csmK8N3J415dpFghbBxRf0eblPk4DBP8xwGfDSo2ZtXN9iIbyFY8inRO0WGE9h4jGq Ne8w== X-Gm-Message-State: AOAM532W8c6SJXr0FCe6Wfr4fUoA+bMTCBlrVzYrRPJCl+yrrx3iXg3w pSxelXYsio3j4NmJgmcz86c= X-Received: by 2002:a17:902:ff16:: with SMTP id f22mr10219128plj.269.1595946850409; Tue, 28 Jul 2020 07:34:10 -0700 (PDT) Received: from server.roeck-us.net ([2600:1700:e321:62f0:329c:23ff:fee3:9d7c]) by smtp.gmail.com with ESMTPSA id d29sm17673991pgb.54.2020.07.28.07.34.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 28 Jul 2020 07:34:09 -0700 (PDT) Subject: Re: [PATCH 1/2] watchdog: imx7ulp: Strictly follow the sequence for wdog operations To: Anson Huang , wim@linux-watchdog.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-watchdog@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Linux-imx@nxp.com References: <1595918567-2017-1-git-send-email-Anson.Huang@nxp.com> From: Guenter Roeck Autocrypt: addr=linux@roeck-us.net; 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Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <1595918567-2017-1-git-send-email-Anson.Huang@nxp.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 7/27/20 11:42 PM, Anson Huang wrote: > According to reference manual, the i.MX7ULP WDOG's operations should > follow below sequence: > > 1. disable global interrupts; > 2. unlock the wdog and wait unlock bit set; > 3. reconfigure the wdog and wait for reconfiguration bit set; > 4. enabel global interrupts. > > Strictly follow the recommended sequence can make it more robust. > > Signed-off-by: Anson Huang > --- > drivers/watchdog/imx7ulp_wdt.c | 29 +++++++++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/drivers/watchdog/imx7ulp_wdt.c b/drivers/watchdog/imx7ulp_wdt.c > index 7993c8c..b414ecf 100644 > --- a/drivers/watchdog/imx7ulp_wdt.c > +++ b/drivers/watchdog/imx7ulp_wdt.c > @@ -4,6 +4,7 @@ > */ > > #include > +#include > #include > #include > #include > @@ -48,17 +49,32 @@ struct imx7ulp_wdt_device { > struct clk *clk; > }; > > +static inline void imx7ulp_wdt_wait(void __iomem *base, u32 mask) > +{ > + int retries = 100; > + > + do { > + if (readl_relaxed(base + WDOG_CS) & mask) > + return; > + usleep_range(200, 1000); > + } while (retries--); Sleep with interrupts disabled ? I can not imagine that this works well in a single CPU system. On top of that, it seems quite pointless. Either you don't want to be interrupted or you do, but sleeping with interrupts disabled really doesn't make sense. And does it really take 200-1000 uS for the watchdog subsystem to react, and sometimes up to 200 * 100 = 20 mS ? That seems highly unlikely. If such a delay loop is indeed needed, it should be limited by a time, not by number of repetitions. Unless there is evidence that there is a problem that needs to be solved, I am not going to accept this code. Thanks, Guenter > +} > + > static void imx7ulp_wdt_enable(struct watchdog_device *wdog, bool enable) > { > struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog); > > u32 val = readl(wdt->base + WDOG_CS); > > + local_irq_disable(); > writel(UNLOCK, wdt->base + WDOG_CNT); > + imx7ulp_wdt_wait(wdt->base, WDOG_CS_ULK); > if (enable) > writel(val | WDOG_CS_EN, wdt->base + WDOG_CS); > else > writel(val & ~WDOG_CS_EN, wdt->base + WDOG_CS); > + imx7ulp_wdt_wait(wdt->base, WDOG_CS_RCS); > + local_irq_enable(); > } > > static bool imx7ulp_wdt_is_enabled(void __iomem *base) > @@ -72,7 +88,12 @@ static int imx7ulp_wdt_ping(struct watchdog_device *wdog) > { > struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog); > > + local_irq_disable(); > + writel(UNLOCK, wdt->base + WDOG_CNT); > + imx7ulp_wdt_wait(wdt->base, WDOG_CS_ULK); > writel(REFRESH, wdt->base + WDOG_CNT); > + imx7ulp_wdt_wait(wdt->base, WDOG_CS_RCS); > + local_irq_enable(); > > return 0; > } > @@ -98,8 +119,12 @@ static int imx7ulp_wdt_set_timeout(struct watchdog_device *wdog, > struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog); > u32 val = WDOG_CLOCK_RATE * timeout; > > + local_irq_disable(); > writel(UNLOCK, wdt->base + WDOG_CNT); > + imx7ulp_wdt_wait(wdt->base, WDOG_CS_ULK); > writel(val, wdt->base + WDOG_TOVAL); > + imx7ulp_wdt_wait(wdt->base, WDOG_CS_RCS); > + local_irq_enable(); > > wdog->timeout = timeout; > > @@ -140,15 +165,19 @@ static void imx7ulp_wdt_init(void __iomem *base, unsigned int timeout) > { > u32 val; > > + local_irq_disable(); > /* unlock the wdog for reconfiguration */ > writel_relaxed(UNLOCK_SEQ0, base + WDOG_CNT); > writel_relaxed(UNLOCK_SEQ1, base + WDOG_CNT); > + imx7ulp_wdt_wait(base, WDOG_CS_ULK); > > /* set an initial timeout value in TOVAL */ > writel(timeout, base + WDOG_TOVAL); > /* enable 32bit command sequence and reconfigure */ > val = WDOG_CS_CMD32EN | WDOG_CS_CLK | WDOG_CS_UPDATE; > writel(val, base + WDOG_CS); > + imx7ulp_wdt_wait(base, WDOG_CS_RCS); > + local_irq_enable(); > } > > static void imx7ulp_wdt_action(void *data) >