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[23.128.96.18]) by mx.google.com with ESMTP id ss20si7333967ejb.700.2020.07.28.07.58.50; Tue, 28 Jul 2020 07:59:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@raspberrypi.com header.s=google header.b=I6r7eI3O; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=raspberrypi.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730549AbgG1O5k (ORCPT + 99 others); Tue, 28 Jul 2020 10:57:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39942 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730483AbgG1O5i (ORCPT ); Tue, 28 Jul 2020 10:57:38 -0400 Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F5E0C061794 for ; Tue, 28 Jul 2020 07:57:38 -0700 (PDT) Received: by mail-wr1-x441.google.com with SMTP id f1so18057809wro.2 for ; Tue, 28 Jul 2020 07:57:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=raspberrypi.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=BwhNWR8x4sReBUnXjkKAZ+VUi9i5Kb9McNJ2lAFUYVE=; b=I6r7eI3O9VehcrKADawlnXf0PAyUWwxAU3XCL5cRdAeuursNuOJMO+HtHbxlxYS1Xv AzghH5B+Pp1ChD3vptP4ouSznOVU5WsOSWiY3TRQYDooWtp7UT99tXpv23Gg1Bqa2WX2 z1pUy07I5jdbs76FEVP0aD/lpF/GMVebXdg4fTZTUO+hCMH+7OuECwRUGyAqGNP4gaJO zpWnVoWVrt6knZRcHhO4EW6P7uM7luOEO1Sg660qoKgSbVpSJ4l2iVXZkMP5dsQH5pGn 99ojDgiGyDTuVsbhLGwQLTFT7o/ZxBfaBw56hnChQALvfqWdAptkdI+H86IJaeo63E+1 BgOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=BwhNWR8x4sReBUnXjkKAZ+VUi9i5Kb9McNJ2lAFUYVE=; b=P/Q4hud3gI2FlOSOqE+Fvksyxj8q0yUhH5Gpc3Bgh+p9C95dR6sVmE5iEnG00Q753n si4p4P4JYzvE8wHG3x+HEHu+YxCAdPJmT6xuLuK2lkZV/MKnvcv8Cc6lUYnvJMzWPBWR 9G918ARsxHQGqavFpShYqfPCtu1sbv9w7blfglB9KGZ4aEiUmYWjuMVMr6VRYfmWHD5c P/UAtccOTqAbEDf5ine/xZMwf9Z4FikWeEXhIgjrzQ9LjOGzyqO1bJJoHvBYwrk98IHQ Nm/Uh0meKnmBibs3ZQUkiCeGT5Ma2SO/ZcL7t0bUuv7k3A9UUTpjs9C2mVEwt0JtIY8w fS8A== X-Gm-Message-State: AOAM531DpmuIKw2deRzf7XFBPGj7qCYuZQ4ltGDSQ/Atjps2Q7CcFtJ4 1npCKsl4CeGe7dIrMANwTQIdG70RNc/3fZ64t8NDxA== X-Received: by 2002:adf:fdce:: with SMTP id i14mr20006305wrs.273.1595948257404; Tue, 28 Jul 2020 07:57:37 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Dave Stevenson Date: Tue, 28 Jul 2020 15:57:22 +0100 Message-ID: Subject: Re: [PATCH v4 63/78] drm/vc4: hdmi: Use clk_set_min_rate instead To: Maxime Ripard Cc: Nicolas Saenz Julienne , Eric Anholt , DRI Development , linux-rpi-kernel@lists.infradead.org, bcm-kernel-feedback-list@broadcom.com, linux-arm-kernel@lists.infradead.org, LKML , Tim Gover , Phil Elwell Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Maxime On Wed, 8 Jul 2020 at 18:44, Maxime Ripard wrote: > > The HSM clock needs to be running at 101% the pixel clock of the HDMI > controller, however it's shared between the two HDMI controllers, which > means that if the resolutions are different between the two HDMI > controllers, and the lowest resolution is on the second (in enable order) > controller, the first HDMI controller will end up with a smaller than > expected clock rate. > > Since we don't really need an exact frequency there, we can simply change > the minimum rate we expect instead. > > Signed-off-by: Maxime Ripard Reviewed-by: Dave Stevenson > --- > drivers/gpu/drm/vc4/vc4_hdmi.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c > index 9f30fab744f2..d99188c90ff9 100644 > --- a/drivers/gpu/drm/vc4/vc4_hdmi.c > +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c > @@ -462,7 +462,7 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) > * pixel clock, but HSM ends up being the limiting factor. > */ > hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101); > - ret = clk_set_rate(vc4_hdmi->hsm_clock, hsm_rate); > + ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); > if (ret) { > DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); > return; > -- > git-series 0.9.1