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[23.128.96.18]) by mx.google.com with ESMTP id g12si7703397edv.266.2020.07.28.08.10.02; Tue, 28 Jul 2020 08:10:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@raspberrypi.com header.s=google header.b=VTagqeDR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=raspberrypi.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730676AbgG1PHJ (ORCPT + 99 others); Tue, 28 Jul 2020 11:07:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41416 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730505AbgG1PHJ (ORCPT ); Tue, 28 Jul 2020 11:07:09 -0400 Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09D0EC061794 for ; Tue, 28 Jul 2020 08:07:09 -0700 (PDT) Received: by mail-wr1-x444.google.com with SMTP id a14so18658716wra.5 for ; Tue, 28 Jul 2020 08:07:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=raspberrypi.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=W/YdhzEx/vyaHEVhqUuCRX7czWchwkSBVhpXRtjSYY4=; b=VTagqeDR8jA/cF11iGP906j2K3kIJGUg0PT91VJQtmmZWW40RJOhkg3WHkLVXNY3SN 8kZL8SgF28l5FAI1pi6of5htR3Sku6yW86xTYzKWrTQl61N9+/x2/WZD5sGraNT7KJQL ix+K3lboyDRkQZM2P146zwHgkvOSDIZZU9Fo0omMt4cNlJeM0gIo045JbvVe3Y/1SmeG yZMt9nPrwBdeiAyd9MzuBGM0VPDpTspHJgnGIXCU1guC4RPPMgbCos1Z86nAd3DEH7H2 Khv5iijZps9LdpFz9ub/q7nEwMs8O1ca+kwQRiAgm8aom4oubq+9tzIoc/GEghsZE8b3 lOJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=W/YdhzEx/vyaHEVhqUuCRX7czWchwkSBVhpXRtjSYY4=; b=FBcjjzqsUFWYOqj7b5CHob4cTGt1JGLrrtzq7QM0f2cB747+E48Hssc0wmmpAvt456 E9De8lRmIW/rOdDZs6YTsDVOX57QIipAyOo5vyC3TzmwBNDaYKfemhmJmTSV4+B/kfYW 0AC3fgWRf0gK77bNJwb50MK5p6wGNBSXAbo30hGzwBMUkQ6dZjtd9dpJgSegUnexDM3D I548qhvsXKLu6fD2zED/r14SF+xqCmf6S1brtn3JAoKA+ROs2Fy/m40+X3KhFMIKK/kt WuahzM6w982n2wEjTJL82LB5W72g/IIWk4sKpAo+uYwqLyGtJ6/N0v5Yl1gdimUF1lWq bs5g== X-Gm-Message-State: AOAM532wY00JjkIOihA58bk6+F3aiKB55V+Fa1GriICLhb2b4k/JLqH5 pb4wGY0Bjph4/r09AauF/VAxhqXL+ddHJIog2avIfg== X-Received: by 2002:a5d:5383:: with SMTP id d3mr18384224wrv.42.1595948827769; Tue, 28 Jul 2020 08:07:07 -0700 (PDT) MIME-Version: 1.0 References: <06921938439fdf7da952fb8d148932fc9403f82a.1594230107.git-series.maxime@cerno.tech> In-Reply-To: <06921938439fdf7da952fb8d148932fc9403f82a.1594230107.git-series.maxime@cerno.tech> From: Dave Stevenson Date: Tue, 28 Jul 2020 16:06:48 +0100 Message-ID: Subject: Re: [PATCH v4 72/78] drm/vc4: hdmi: Do the VID_CTL configuration at once To: Maxime Ripard Cc: Nicolas Saenz Julienne , Eric Anholt , DRI Development , linux-rpi-kernel@lists.infradead.org, bcm-kernel-feedback-list@broadcom.com, linux-arm-kernel@lists.infradead.org, LKML , Tim Gover , Phil Elwell Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Maxime On Wed, 8 Jul 2020 at 18:44, Maxime Ripard wrote: > > The VID_CTL setup is done in several places in the driver even though it's > not really required. Let's simplify it a bit to do the configuration in one > go. > > Signed-off-by: Maxime Ripard Reviewed-by: Dave Stevenson > --- > drivers/gpu/drm/vc4/vc4_hdmi.c | 14 ++++++-------- > 1 file changed, 6 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c > index bbe521ab000b..f56a718a3643 100644 > --- a/drivers/gpu/drm/vc4/vc4_hdmi.c > +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c > @@ -428,10 +428,6 @@ static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, > > HDMI_WRITE(HDMI_VERTB0, vertb_even); > HDMI_WRITE(HDMI_VERTB1, vertb); > - > - HDMI_WRITE(HDMI_VID_CTL, > - (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | > - (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); > } > > static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi) > @@ -520,8 +516,6 @@ static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder) > if (vc4_hdmi->variant->phy_init) > vc4_hdmi->variant->phy_init(vc4_hdmi, mode); > > - HDMI_WRITE(HDMI_VID_CTL, 0); > - > HDMI_WRITE(HDMI_SCHEDULER_CONTROL, > HDMI_READ(HDMI_SCHEDULER_CONTROL) | > VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | > @@ -555,15 +549,19 @@ static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder) > > static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder) > { > + struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; > struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); > struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); > + bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; > + bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; > int ret; > > HDMI_WRITE(HDMI_VID_CTL, > - HDMI_READ(HDMI_VID_CTL) | > VC4_HD_VID_CTL_ENABLE | > VC4_HD_VID_CTL_UNDERFLOW_ENABLE | > - VC4_HD_VID_CTL_FRAME_COUNTER_RESET); > + VC4_HD_VID_CTL_FRAME_COUNTER_RESET | > + (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | > + (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); > > if (vc4_encoder->hdmi_monitor) { > HDMI_WRITE(HDMI_SCHEDULER_CONTROL, > -- > git-series 0.9.1