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Date:   Wed, 29 Jul 2020 11:11:54 +0200
From:   peterz@infradead.org
To:     Andy Lutomirski <luto@kernel.org>
Cc:     Gabriel Krisman Bertazi <krisman@collabora.com>,
        Christoph Hellwig <hch@lst.de>,
        Thomas Gleixner <tglx@linutronix.de>,
        Kees Cook <keescook@chromium.org>, X86 ML <x86@kernel.org>,
        LKML <linux-kernel@vger.kernel.org>, kernel@collabora.com
Subject: Re: [PATCH 2/6] arch: x86: Wrap TIF_IA32 checks
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On Tue, Jul 28, 2020 at 08:43:27PM -0700, Andy Lutomirski wrote:
> On Tue, Jul 28, 2020 at 1:22 PM Gabriel Krisman Bertazi

> > diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
> > index dc43cc124e09..27d1cc1f3d05 100644
> > --- a/arch/x86/events/intel/ds.c
> > +++ b/arch/x86/events/intel/ds.c
> > @@ -1261,7 +1261,7 @@ static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
> >                 old_to = to;
> >
> >  #ifdef CONFIG_X86_64
> > -               is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
> > +               is_64bit = kernel_ip(to) || !TASK_IA32(current);
> 
> PeterZ, does PEBS not give us a CPL?  Is it really just IP?
> 
> Anyway, this should probably be:
> 
> is_64bit = kernel_ip(to) || user_64bit_mode(regs) || !user_mode(regs);

Correct, PEBS doesn't have the segment registers and we get to guess :/
Look at the various pebs_record_* structures in
arch/x86/events/intel/ds.c.

That said, in fixup_ip() we're guaranteed to be in the same process, so
unless the task does really funny things like switch mode between
triggering the assist and getting the PMI, we ought to be able to trust
regs.