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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id a134sm6526030wmd.17.2020.07.29.08.44.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jul 2020 08:44:06 -0700 (PDT) From: Jerome Brunet To: Neil Armstrong , linux-clk@vger.kernel.org Cc: Jerome Brunet , Kevin Hilman , linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 0/3] clk: meson: axg-audio: fix tdmout sclk inverter Date: Wed, 29 Jul 2020 17:43:56 +0200 Message-Id: <20200729154359.1983085-1-jbrunet@baylibre.com> X-Mailer: git-send-email 2.25.4 MIME-Version: 1.0 X-Patchwork-Bot: notify Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The patchset fixes a problem with TDMOUT sclk inverter found on the g12a and following SoCs. On the the axg, a single bit was enough to drive the inverter. On the g12a a bit was added to, somehow, change how the clock is sampled. For the inverter to behave as intended, the new bit should be the inverse of the inverter bit at all time. Quite a lot of lines for a single bit ... Jerome Brunet (3): clk: meson: add sclk-ws driver clk: meson: axg-audio: separate axg and g12a regmap tables clk: meson: axg-audio: fix g12a tdmout sclk inverter drivers/clk/meson/axg-audio.c | 214 +++++++++++++++++++++++++++++----- drivers/clk/meson/clk-phase.c | 56 +++++++++ drivers/clk/meson/clk-phase.h | 6 + 3 files changed, 246 insertions(+), 30 deletions(-) -- 2.25.4