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From:   Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
To:     bhelgaas@google.com, rjui@broadcom.com, sbranden@broadcom.com,
        f.fainelli@gmail.com
Cc:     linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
        Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
Subject: [PATCH 1/3] PCI: iproc: Add bus number parameter to read/write functions
Date:   Thu, 30 Jul 2020 15:37:45 +1200
Message-Id: <20200730033747.18931-1-mark.tomlinson@alliedtelesis.co.nz>
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This makes the read/write functions more generic, allowing them to be
used from other places.

Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
---
 drivers/pci/controller/pcie-iproc.c | 23 ++++++++++++-----------
 1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/pci/controller/pcie-iproc.c b/drivers/pci/controller=
/pcie-iproc.c
index 8c7f875acf7f..2c836eede42c 100644
--- a/drivers/pci/controller/pcie-iproc.c
+++ b/drivers/pci/controller/pcie-iproc.c
@@ -660,13 +660,13 @@ static void __iomem *iproc_pcie_bus_map_cfg_bus(str=
uct pci_bus *bus,
 				      where);
 }
=20
-static int iproc_pci_raw_config_read32(struct iproc_pcie *pcie,
+static int iproc_pci_raw_config_read32(struct iproc_pcie *pcie, int busn=
o,
 				       unsigned int devfn, int where,
 				       int size, u32 *val)
 {
 	void __iomem *addr;
=20
-	addr =3D iproc_pcie_map_cfg_bus(pcie, 0, devfn, where & ~0x3);
+	addr =3D iproc_pcie_map_cfg_bus(pcie, busno, devfn, where & ~0x3);
 	if (!addr) {
 		*val =3D ~0;
 		return PCIBIOS_DEVICE_NOT_FOUND;
@@ -680,14 +680,14 @@ static int iproc_pci_raw_config_read32(struct iproc=
_pcie *pcie,
 	return PCIBIOS_SUCCESSFUL;
 }
=20
-static int iproc_pci_raw_config_write32(struct iproc_pcie *pcie,
+static int iproc_pci_raw_config_write32(struct iproc_pcie *pcie, int bus=
no,
 					unsigned int devfn, int where,
 					int size, u32 val)
 {
 	void __iomem *addr;
 	u32 mask, tmp;
=20
-	addr =3D iproc_pcie_map_cfg_bus(pcie, 0, devfn, where & ~0x3);
+	addr =3D iproc_pcie_map_cfg_bus(pcie, busno, devfn, where & ~0x3);
 	if (!addr)
 		return PCIBIOS_DEVICE_NOT_FOUND;
=20
@@ -793,7 +793,7 @@ static int iproc_pcie_check_link(struct iproc_pcie *p=
cie)
 	}
=20
 	/* make sure we are not in EP mode */
-	iproc_pci_raw_config_read32(pcie, 0, PCI_HEADER_TYPE, 1, &hdr_type);
+	iproc_pci_raw_config_read32(pcie, 0, 0, PCI_HEADER_TYPE, 1, &hdr_type);
 	if ((hdr_type & 0x7f) !=3D PCI_HEADER_TYPE_BRIDGE) {
 		dev_err(dev, "in EP mode, hdr=3D%#02x\n", hdr_type);
 		return -EFAULT;
@@ -803,15 +803,16 @@ static int iproc_pcie_check_link(struct iproc_pcie =
*pcie)
 #define PCI_BRIDGE_CTRL_REG_OFFSET	0x43c
 #define PCI_CLASS_BRIDGE_MASK		0xffff00
 #define PCI_CLASS_BRIDGE_SHIFT		8
-	iproc_pci_raw_config_read32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET,
+	iproc_pci_raw_config_read32(pcie, 0, 0, PCI_BRIDGE_CTRL_REG_OFFSET,
 				    4, &class);
 	class &=3D ~PCI_CLASS_BRIDGE_MASK;
 	class |=3D (PCI_CLASS_BRIDGE_PCI << PCI_CLASS_BRIDGE_SHIFT);
-	iproc_pci_raw_config_write32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET,
+	iproc_pci_raw_config_write32(pcie, 0, 0, PCI_BRIDGE_CTRL_REG_OFFSET,
 				     4, class);
=20
 	/* check link status to see if link is active */
-	iproc_pci_raw_config_read32(pcie, 0, IPROC_PCI_EXP_CAP + PCI_EXP_LNKSTA=
,
+	iproc_pci_raw_config_read32(pcie, 0, 0,
+				    IPROC_PCI_EXP_CAP + PCI_EXP_LNKSTA,
 				    2, &link_status);
 	if (link_status & PCI_EXP_LNKSTA_NLW)
 		link_is_active =3D true;
@@ -821,19 +822,19 @@ static int iproc_pcie_check_link(struct iproc_pcie =
*pcie)
 #define PCI_TARGET_LINK_SPEED_MASK	0xf
 #define PCI_TARGET_LINK_SPEED_GEN2	0x2
 #define PCI_TARGET_LINK_SPEED_GEN1	0x1
-		iproc_pci_raw_config_read32(pcie, 0,
+		iproc_pci_raw_config_read32(pcie, 0, 0,
 					    IPROC_PCI_EXP_CAP + PCI_EXP_LNKCTL2,
 					    4, &link_ctrl);
 		if ((link_ctrl & PCI_TARGET_LINK_SPEED_MASK) =3D=3D
 		    PCI_TARGET_LINK_SPEED_GEN2) {
 			link_ctrl &=3D ~PCI_TARGET_LINK_SPEED_MASK;
 			link_ctrl |=3D PCI_TARGET_LINK_SPEED_GEN1;
-			iproc_pci_raw_config_write32(pcie, 0,
+			iproc_pci_raw_config_write32(pcie, 0, 0,
 					IPROC_PCI_EXP_CAP + PCI_EXP_LNKCTL2,
 					4, link_ctrl);
 			msleep(100);
=20
-			iproc_pci_raw_config_read32(pcie, 0,
+			iproc_pci_raw_config_read32(pcie, 0, 0,
 					IPROC_PCI_EXP_CAP + PCI_EXP_LNKSTA,
 					2, &link_status);
 			if (link_status & PCI_EXP_LNKSTA_NLW)
--=20
2.28.0