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Fri, 31 Jul 2020 12:28:53 +0000 From: "Lu, Brent" To: Takashi Iwai , Pierre-Louis Bossart CC: "alsa-devel@alsa-project.org" , "Guennadi Liakhovetski" , "Rojewski, Cezary" , Kai Vehmanen , Kuninori Morimoto , Jie Yang , Takashi Iwai , "linux-kernel@vger.kernel.org" , Liam Girdwood , Sam McNally , "Mark Brown" , Ranjani Sridharan , Daniel Stuart , Andy Shevchenko , Yu-Hsuan Hsu , Damian van Soelen Subject: RE: [PATCH 2/2] ASoC: Intel: Add period size constraint on strago board Thread-Topic: [PATCH 2/2] ASoC: Intel: Add period size constraint on strago board Thread-Index: AQHWZZiWhH0ib4T+aUeOy2BFXbTqlKkemFEAgAErLkCAAH1RAIAAGJyAgAFHf7A= Date: Fri, 31 Jul 2020 12:28:53 +0000 Message-ID: References: <1596020585-11517-1-git-send-email-brent.lu@intel.com> <1596020585-11517-3-git-send-email-brent.lu@intel.com> <4fe97f63-e552-3b2f-803c-53894b196bfd@linux.intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.5.1.3 dlp-product: dlpe-windows dlp-reaction: no-action authentication-results: suse.de; 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x-ms-exchange-antispam-messagedata: 104KWf4as863x57Jj4ol0LqNulyEKiXoPNf+0r0i1WGTOgbrnGizmJavGsWSOjyteZ3ZL6PFQhHfGPMsnlgfQ5F4Sb0CXcKdXeSwqn1KOMT2Yi2ehp8teqCamcOAfddMbLUFKh01AARhgHJ8BtrUIo4iEuaAnrcWhOSqDM8rvhSPAgPMgB7m6Up60Y9wDr6TiXl+7ts458Jym/PmxPtBZpd+4YA49sdJnrXugBoSyRezLqQHCTj85YtQTyaLI5iDCd46SCuqJCn6CeUN/do167uVGgznAe5PBYaXr9Pyk3epgmtQ1dNh3+EsnjQuBTEULqcP/ATq2O50lkO7wBk748Iks1UL2KFCGDgdgwqENvMdmHMGZoY2QfTsCgOVZDv4CH9Ffsjg8npNXAqxdrBA2L68UvLE0X2QPLag+scY9wjb+fhuPSzUwADKEoNAyOyPD1sQfXxbU1SyvHKQ3MGToJZlkFNdFq6Tv2sS56hi5cOtK8x1MpxqYwK4QIvz3dgmJKZgbBOg1llFxHL/9sXNCu5LE4Gmxg9JZWWB+6yHwOB9n8ij2ABKDlF/ZwIOITG9s5D8G8ivNrM1EvgrsPFx4Bgde0XflHpexWFHKvq3/keM39LocJHY9bcJLSIOC2A2WRYj8MSNReAt3nSueARiyA== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM6PR11MB3642.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8acd0fd9-ca6b-4be5-2274-08d8354d4972 X-MS-Exchange-CrossTenant-originalarrivaltime: 31 Jul 2020 12:28:53.3216 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: OSJv6TuYtVE15VCpdceesGNZ4aVDGbB/pteWxre+43B3j5QQkvqvL2eThsE+HH0D6aHaC9+rRwgeBp90Nxvhfg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR11MB3785 X-OriginatorOrg: intel.com Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org >=20 > If the 1ms alignment is the condition, it can be better with a different > hw_params constraint. We can use > snd_pcm_hw_constraint_step() for such a purpose. Will fix. Thanks. Regards, Brent >=20 >=20 > thanks, >=20 > Takashi