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From:   Chun-Kuang Hu <chunkuang.hu@kernel.org>
Date:   Fri, 31 Jul 2020 23:55:23 +0800
Message-ID: <CAAOTY_-3vs9VdAs3RHc_-MQJ7HbmqXKgULC_H0grr3q7oNDxMQ@mail.gmail.com>
Subject: Re: [PATCH v4 2/2] soc: mediatek: add mtk-devapc driver
To:     Neal Liu <neal.liu@mediatek.com>
Cc:     Chun-Kuang Hu <chunkuang.hu@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Matthias Brugger <matthias.bgg@gmail.com>,
        devicetree@vger.kernel.org,
        wsd_upstream <wsd_upstream@mediatek.com>,
        lkml <linux-kernel@vger.kernel.org>,
        "moderated list:ARM/Mediatek SoC support" 
        <linux-mediatek@lists.infradead.org>,
        Linux ARM <linux-arm-kernel@lists.infradead.org>
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Hi, Neal:

Neal Liu <neal.liu@mediatek.com> =E6=96=BC 2020=E5=B9=B47=E6=9C=8831=E6=97=
=A5 =E9=80=B1=E4=BA=94 =E4=B8=8A=E5=8D=8810:52=E5=AF=AB=E9=81=93=EF=BC=9A
>
> Hi Chun-Kuang,
>
> On Fri, 2020-07-31 at 00:14 +0800, Chun-Kuang Hu wrote:
> > Hi, Neal:
> >
> > Neal Liu <neal.liu@mediatek.com> =E6=96=BC 2020=E5=B9=B47=E6=9C=8829=E6=
=97=A5 =E9=80=B1=E4=B8=89 =E4=B8=8B=E5=8D=884:29=E5=AF=AB=E9=81=93=EF=BC=9A
> > >
> > > MediaTek bus fabric provides TrustZone security support and data
> > > protection to prevent slaves from being accessed by unexpected
> > > masters.
> > > The security violation is logged and sent to the processor for
> > > further analysis or countermeasures.
> > >
> > > Any occurrence of security violation would raise an interrupt, and
> > > it will be handled by mtk-devapc driver. The violation
> > > information is printed in order to find the murderer.
> > >
> > > Signed-off-by: Neal Liu <neal.liu@mediatek.com>
> > > ---
> >
> > [snip]
> >
> > > +
> > > +/*
> > > + * devapc_extract_vio_dbg - extract full violation information after=
 doing
> > > + *                          shift mechanism.
> > > + */
> > > +static void devapc_extract_vio_dbg(struct mtk_devapc_context *ctx)
> > > +{
> > > +       const struct mtk_devapc_vio_dbgs *vio_dbgs;
> > > +       struct mtk_devapc_vio_info *vio_info;
> > > +       void __iomem *vio_dbg0_reg;
> > > +       void __iomem *vio_dbg1_reg;
> > > +       u32 dbg0;
> > > +
> > > +       vio_dbg0_reg =3D ctx->devapc_pd_base + ctx->offset->vio_dbg0;
> > > +       vio_dbg1_reg =3D ctx->devapc_pd_base + ctx->offset->vio_dbg1;
> > > +
> > > +       vio_dbgs =3D ctx->vio_dbgs;
> > > +       vio_info =3D ctx->vio_info;
> > > +
> > > +       /* Starts to extract violation information */
> > > +       dbg0 =3D readl(vio_dbg0_reg);
> > > +       vio_info->vio_addr =3D readl(vio_dbg1_reg);
> > > +
> > > +       vio_info->master_id =3D (dbg0 & vio_dbgs->mstid.mask) >>
> > > +                             vio_dbgs->mstid.start;
> > > +       vio_info->domain_id =3D (dbg0 & vio_dbgs->dmnid.mask) >>
> > > +                             vio_dbgs->dmnid.start;
> > > +       vio_info->write =3D ((dbg0 & vio_dbgs->vio_w.mask) >>
> > > +                           vio_dbgs->vio_w.start) =3D=3D 1;
> > > +       vio_info->read =3D ((dbg0 & vio_dbgs->vio_r.mask) >>
> > > +                         vio_dbgs->vio_r.start) =3D=3D 1;
> > > +       vio_info->vio_addr_high =3D (dbg0 & vio_dbgs->addr_h.mask) >>
> > > +                                 vio_dbgs->addr_h.start;
> >
> >
> > I would like to define the type of ctx->vio_info to be
> >
> > struct mtk_devapc_vio_dbgs {
> >     u32 mstid:16;
> >     u32 dmnid:6;
> >     u32 vio_w:1;
> >     u32 vio_r:1;
> >     u32 addr_h:4;
> >     u32 resv:4;
> > };
> >
> > so the code would like the simple way
> >
> > ctx->vio_info =3D (struct mtk_devapc_vio_dbgs)readl(vio_dbg1_reg);
> >
>
> This idea looks great! Is there any possible to pass the bit layout by
> DT data, and still make this operation simple?
> Why am I asking this question is because this bit layout is platform
> dependent.

I doubt these info would be in a single 32-bits register for all
future SoC. If they are not in single 32-bits register, you may create
a vio_dbgs_type in DT data, and the code may be

if (ctx->vio_dbgs_type =3D=3D VIO_DBGS_TYPE_MTxxxx) {
    ctx->vio_info =3D (struct mtk_devapc_vio_dbgs)readl(vio_dbg1_reg);
} else if (ctx->vio_dbgs_type =3D=3D VIO_DBGS_TYPE_MTyyyy) {
    ctx->vio_info->mstid =3D readl(vio_mstid_reg);
    ctx->vio_info->dmnid =3D readl(vio_dmnid_reg);
    ctx->vio_info->vio_w =3D readl(vio_vio_w_reg);
    ctx->vio_info->vio_r =3D readl(vio_vio_r_reg);
}

I think we need not to consider how the future would be. Once the
second SoC driver is upstreaming, we could find out the best solution
for it.

Regards,
Chun-Kuang.

>
> > Regards,
> > Chun-Kuang.
> >
> > > +
> > > +       devapc_vio_info_print(ctx);
> > > +}
> > > +
>