Received: by 2002:a05:6a10:a0d1:0:0:0:0 with SMTP id j17csp2307896pxa; Mon, 3 Aug 2020 12:45:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzAWlZ+3W+jMUyLdinh2ipjSodchAf8KTrsBYX74JnGE3jXfKq7HRjk3I7BrEAYiM4b8uqD X-Received: by 2002:a05:6402:13d4:: with SMTP id a20mr2369933edx.161.1596483905099; Mon, 03 Aug 2020 12:45:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1596483905; cv=none; d=google.com; s=arc-20160816; b=H2J+zvNEf3g6XmE1ZJP+Hw9CjlWiGF/jwRdtHlMl9soYyt6CyCRJanli1x7j3Nmije PVnU0FeC2izPpCIQzLR8tORLzKh8xJQ3flK3dRNPPM+55nW5pd+CDsredg9RSFOpvyVu ZmZHpbLbsN4eTGWJw0sM4DXVN8/dd4My1keM7Zks85ynelAmyFaE9Yd3T6UIWunm6jP7 K+9CsMdT2DZ+I8nfggu1+pdSI31OUEI7LPR/jC8iCIoLUGDB5ANVmE/1u0XaJkLpNfzq WsWtsSPKZdse8vn50J7dspV3vCHMf5kBsrnRGoe0bAP72BFiAVo8cd4UGp3HVs5fdfxM LiBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:dkim-signature:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from; bh=eFc2VU5GTK3y8YU8lvXMTIrju/5qbDsv3weenC955gY=; b=d/Tla5x3+1GuGrIEuMBqQhNeCu5PRmlAI8H7G+A/6AbIIBYKgiqXXgOICcFr3O4ruy j6mOojmtNQtW75Ejp+++o4/ZYoGa1fwi/ehpGdTia7sfygpsKSi+nZCT0IlkvRqmI5gG S4PMtuPZqoKtCzK6vdbviqnvObE4QrBfuVRIJnM7iOnUxyvU3XXkjhfHvH2FAxhgRdt9 vw7fka+RFyIJdRx1mIA+OS4AXTls7uB0LeEDExAKONyHXmjEux+iVYLN0DPJ+E8BdrNR A/rtmkiIxXWT4mENgZ6Rp8zHug/yCgIncAw5hAF0vaBxMNhd6BJWUCCC6ux5lJcWOd0J EITw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=axOc1qr0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id z12si5954426edx.530.2020.08.03.12.44.42; Mon, 03 Aug 2020 12:45:05 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=axOc1qr0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728534AbgHCToc (ORCPT + 99 others); Mon, 3 Aug 2020 15:44:32 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:6349 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726906AbgHCToc (ORCPT ); Mon, 3 Aug 2020 15:44:32 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 03 Aug 2020 12:44:18 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 03 Aug 2020 12:44:32 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 03 Aug 2020 12:44:32 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 3 Aug 2020 19:44:31 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 3 Aug 2020 19:44:31 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.167.221]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Mon, 03 Aug 2020 12:44:30 -0700 From: Sowjanya Komatineni To: , , , , CC: , , , , Subject: [PATCH v1 4/6] arm64: tegra: Add missing timeout clock to Tegra186 SDMMC nodes Date: Mon, 3 Aug 2020 12:44:21 -0700 Message-ID: <1596483863-22153-5-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596483863-22153-1-git-send-email-skomatineni@nvidia.com> References: <1596483863-22153-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1596483858; bh=eFc2VU5GTK3y8YU8lvXMTIrju/5qbDsv3weenC955gY=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=axOc1qr08OYIAXDeOk7G7jvEFPBICz33ZtJTUrItnkjxbRqDG8GXHYy7lNvC1bPqq hyI4LCx7rgPe8B8s/jK1OaFx8kYJm8iLLXn2OJqsH/vsfZTOrdFyDlfTEB3ExPV9id V17Enl0F/ig7FU9z9PxlPT/zFxTEsEBU7STBbmoz0QY7FCyQQ2eDNZoMzxRFGDLSCz nVYYsmcnygc5taLJqaD/tC7mHja9EAl8X0Qsors1OFstXq1EVcgCxIt7XHhlPbbi9o CtvMGkSchAkJpjOlzmJEfykL/JHf8n7FYwdGUgEz1RjuaTYUYWAa0ETbeVbb3mE7S3 MyuU/pmAbUWNg== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org commit 39cb62cb8973 ("arm64: tegra: Add Tegra186 support") Tegra186 uses separate SDMMC_LEGACY_TM clock for data timeout and this clock is not enabled currently which is not recommended. Tegra186 SDMMC advertises 12Mhz as timeout clock frequency in host capability register and uses it by default. So, this clock should be kept enabled by the SDMMC driver. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 34d249d..8eb61dd 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -337,8 +337,9 @@ compatible = "nvidia,tegra186-sdhci"; reg = <0x0 0x03400000 0x0 0x10000>; interrupts = ; - clocks = <&bpmp TEGRA186_CLK_SDMMC1>; - clock-names = "sdhci"; + clocks = <&bpmp TEGRA186_CLK_SDMMC1>, + <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; + clock-names = "sdhci", "tmclk"; resets = <&bpmp TEGRA186_RESET_SDMMC1>; reset-names = "sdhci"; interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, @@ -366,8 +367,9 @@ compatible = "nvidia,tegra186-sdhci"; reg = <0x0 0x03420000 0x0 0x10000>; interrupts = ; - clocks = <&bpmp TEGRA186_CLK_SDMMC2>; - clock-names = "sdhci"; + clocks = <&bpmp TEGRA186_CLK_SDMMC2>, + <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; + clock-names = "sdhci", "tmclk"; resets = <&bpmp TEGRA186_RESET_SDMMC2>; reset-names = "sdhci"; interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, @@ -390,8 +392,9 @@ compatible = "nvidia,tegra186-sdhci"; reg = <0x0 0x03440000 0x0 0x10000>; interrupts = ; - clocks = <&bpmp TEGRA186_CLK_SDMMC3>; - clock-names = "sdhci"; + clocks = <&bpmp TEGRA186_CLK_SDMMC3>, + <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; + clock-names = "sdhci", "tmclk"; resets = <&bpmp TEGRA186_RESET_SDMMC3>; reset-names = "sdhci"; interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, @@ -416,8 +419,9 @@ compatible = "nvidia,tegra186-sdhci"; reg = <0x0 0x03460000 0x0 0x10000>; interrupts = ; - clocks = <&bpmp TEGRA186_CLK_SDMMC4>; - clock-names = "sdhci"; + clocks = <&bpmp TEGRA186_CLK_SDMMC4>, + <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; + clock-names = "sdhci", "tmclk"; assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, <&bpmp TEGRA186_CLK_PLLC4_VCO>; assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; -- 2.7.4