Subject: Re: [PATCH] hptiop: HighPoint RocketRAID 3xxx controller driver
From: Arjan van de Ven <arjan@infradead.org>
To: HighPoint Linux Team <linux@highpoint-tech.com>
Cc: Andrew Morton <akpm@osdl.org>, linux-scsi@vger.kernel.org,
       linux-kernel@vger.kernel.org
In-Reply-To: <041901c677e7$fdd9fbf0$1200a8c0@GMM>
References: <200605122209.k4CM95oW014664@mail.hypersurf.com>
	 <041901c677e7$fdd9fbf0$1200a8c0@GMM>
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Date: Mon, 15 May 2006 08:56:35 +0200
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On Mon, 2006-05-15 at 14:22 +0800, HighPoint Linux Team wrote:
> Could you give more explanation about pci posting flush? When (and why) do we need it?

pci posting is where the chipset internally delays (posts) writes (as
done by writel and such) to see if more writes will come that can then
be combined into one burst. While in practice these queues are finite
(and often have a timeout) it's bad practice to depend on that. The
simplest way to flush out this posting is to do a (dummy) readl() from
the same device. (alternative is to do dma from the device to ram, but
readl() is a lot easier ;)

> In an old posting (http://lkml.org/lkml/2003/5/8/278) said pci posting flush is unnecessary - is it correct?

no not really, not as a general statement.


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