Message-ID: <44682CDB.9080804@garzik.org>
Date: Mon, 15 May 2006 03:25:15 -0400
From: Jeff Garzik <jeff@garzik.org>
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To: Arjan van de Ven <arjan@infradead.org>
CC: HighPoint Linux Team <linux@highpoint-tech.com>,
       Andrew Morton <akpm@osdl.org>, linux-scsi@vger.kernel.org,
       linux-kernel@vger.kernel.org
Subject: Re: [PATCH] hptiop: HighPoint RocketRAID 3xxx controller driver
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Arjan van de Ven wrote:
> On Mon, 2006-05-15 at 14:22 +0800, HighPoint Linux Team wrote:
>> Could you give more explanation about pci posting flush? When (and why) do we need it?
> 
> pci posting is where the chipset internally delays (posts) writes (as
> done by writel and such) to see if more writes will come that can then
> be combined into one burst. While in practice these queues are finite
> (and often have a timeout) it's bad practice to depend on that. The
> simplest way to flush out this posting is to do a (dummy) readl() from
> the same device. (alternative is to do dma from the device to ram, but
> readl() is a lot easier ;)
> 
>> In an old posting (http://lkml.org/lkml/2003/5/8/278) said pci posting flush is unnecessary - is it correct?
> 
> no not really, not as a general statement.

ACK.

Generally speaking, readl() is the best way to ensure that all writes 
have been flushed across various layers of PCI bridges, etc.

It is particularly important to get this right if you are issuing a 
delay (i.e. udelay) after a write.  If the write is not guaranteed to be 
flushed at the time the delay begins, then you are no longer truly 
delaying for the time requested.

	Jeff


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