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Mon, 03 Aug 2020 23:44:43 -0700 From: Amit Sunil Dhamne To: mturquette@baylibre.com, m.tretter@pengutronix.de, sboyd@kernel.org, michal.simek@xilinx.com, mark.rutland@arm.com, linux-clk@vger.kernel.org Cc: rajanv@xilinx.com, jollys@xilinx.com, tejasp@xilinx.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rajan Vaja , Tejas Patel , Amit Sunil Dhamne Subject: [PATCH v3 3/3] clk: zynqmp: Use firmware specific mux clock flags Date: Mon, 3 Aug 2020 23:44:17 -0700 Message-Id: <1596523457-40465-4-git-send-email-amit.sunil.dhamne@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596523457-40465-1-git-send-email-amit.sunil.dhamne@xilinx.com> References: <1596523457-40465-1-git-send-email-amit.sunil.dhamne@xilinx.com> X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email MIME-Version: 1.0 Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: c14797b5-ae1a-4067-b2be-08d83841e319 X-MS-TrafficTypeDiagnostic: DM5PR02MB2185: X-Microsoft-Antispam-PRVS: Content-Transfer-Encoding: quoted-printable X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:813; 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Signed-off-by: Rajan Vaja Signed-off-by: Tejas Patel Signed-off-by: Amit Sunil Dhamne --- drivers/clk/zynqmp/clk-mux-zynqmp.c | 22 +++++++++++++++++++++- drivers/clk/zynqmp/clk-zynqmp.h | 8 ++++++++ 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/clk/zynqmp/clk-mux-zynqmp.c b/drivers/clk/zynqmp/clk-m= ux-zynqmp.c index a49b1c5..8a8c960 100644 --- a/drivers/clk/zynqmp/clk-mux-zynqmp.c +++ b/drivers/clk/zynqmp/clk-mux-zynqmp.c @@ -90,6 +90,26 @@ static const struct clk_ops zynqmp_clk_mux_ro_ops =3D { .get_parent =3D zynqmp_clk_mux_get_parent, }; +static inline unsigned long zynqmp_clk_map_mux_ccf_flags( + const u32 zynqmp_type_flag) +{ + unsigned long ccf_flag =3D 0; + + ccf_flag |=3D (zynqmp_type_flag & ZYNQMP_CLK_MUX_INDEX_ONE) ? + CLK_MUX_INDEX_ONE : 0; + ccf_flag |=3D (zynqmp_type_flag & ZYNQMP_CLK_MUX_INDEX_BIT) ? + CLK_MUX_INDEX_BIT : 0; + ccf_flag |=3D (zynqmp_type_flag & ZYNQMP_CLK_MUX_HIWORD_MASK) ? + CLK_MUX_HIWORD_MASK : 0; + ccf_flag |=3D (zynqmp_type_flag & ZYNQMP_CLK_MUX_READ_ONLY) ? + CLK_MUX_READ_ONLY : 0; + ccf_flag |=3D (zynqmp_type_flag & ZYNQMP_CLK_MUX_ROUND_CLOSEST) ? + CLK_MUX_ROUND_CLOSEST : 0; + ccf_flag |=3D (zynqmp_type_flag & ZYNQMP_CLK_MUX_BIG_ENDIAN) ? + CLK_MUX_BIG_ENDIAN : 0; + return ccf_flag; +} + /** * zynqmp_clk_register_mux() - Register a mux table with the clock * framework @@ -125,7 +145,7 @@ struct clk_hw *zynqmp_clk_register_mux(const char *name= , u32 clk_id, init.parent_names =3D parents; init.num_parents =3D num_parents; - mux->flags =3D nodes->type_flag; + mux->flags =3D zynqmp_clk_map_mux_ccf_flags(nodes->type_flag); mux->hw.init =3D &init; mux->clk_id =3D clk_id; diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqm= p.h index 9b2ff35e..87a2e12 100644 --- a/drivers/clk/zynqmp/clk-zynqmp.h +++ b/drivers/clk/zynqmp/clk-zynqmp.h @@ -41,6 +41,14 @@ #define ZYNQMP_CLK_DIVIDER_READ_ONLY BIT(5) #define ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO BIT(6) +/* Type Flags for mux clock */ +#define ZYNQMP_CLK_MUX_INDEX_ONE BIT(0) +#define ZYNQMP_CLK_MUX_INDEX_BIT BIT(1) +#define ZYNQMP_CLK_MUX_HIWORD_MASK BIT(2) +#define ZYNQMP_CLK_MUX_READ_ONLY BIT(3) +#define ZYNQMP_CLK_MUX_ROUND_CLOSEST BIT(4) +#define ZYNQMP_CLK_MUX_BIG_ENDIAN BIT(5) + enum topology_type { TYPE_INVALID, TYPE_MUX, -- 2.7.4 This email and any attachments are intended for the sole use of the named r= ecipient(s) and contain(s) confidential information that may be proprietary= , privileged or copyrighted under applicable law. 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