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[23.128.96.18]) by mx.google.com with ESMTP id e2si729598edv.492.2020.08.05.00.05.48; Wed, 05 Aug 2020 00:06:11 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@st.com header.s=STMicroelectronics header.b="PRIhE/WW"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=st.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728394AbgHEHFJ (ORCPT + 99 others); Wed, 5 Aug 2020 03:05:09 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:8914 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728363AbgHEHEh (ORCPT ); Wed, 5 Aug 2020 03:04:37 -0400 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 07572SqX030160; Wed, 5 Aug 2020 09:04:21 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=STMicroelectronics; bh=5f/kmG4N622sMrrGFS0Jhu+gX16MgwdDVf5qJCdceBQ=; b=PRIhE/WWA2z7xAjACT5MgmqYL9rp4r/aryLr4UTUHIqp/BAi141gpZ5eNi4SOgqk6KPv sVsCndw+E0LKq9Symouh6wSxpiyaDRexj+VgJolgrMHdlxpKDX5AVmzmAcosbogb/Ud6 5BHCpX5KrAeWvzj7QVQCb7kOFqxoKaXlkRc7J3NCYEdp+fGJP7FnA6vZimNRxJaC6ABC quTSCqtKAEJ0hiwuCTSOEncfaZ2qPUcO22NXExez5f4Uf/Fd+oDvi2rEXWMkEdwYHEgT fs9lBLZBwgHMe75OWp6dUWYOrXTz7yZSIDgH3Nb7gmPbfVBs+1mtWQwXRp71NyPnwekg BA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 32n6hyq7tx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 05 Aug 2020 09:04:21 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id EE32C10002A; Wed, 5 Aug 2020 09:04:20 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag3node2.st.com [10.75.127.8]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id E2F812A4D8E; Wed, 5 Aug 2020 09:04:20 +0200 (CEST) Received: from localhost (10.75.127.49) by SFHDAG3NODE2.st.com (10.75.127.8) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 5 Aug 2020 09:04:20 +0200 From: Alain Volmat To: , CC: , , , , , , , Subject: [PATCH 18/18] spi: stm32h7: ensure message are smaller than max size Date: Wed, 5 Aug 2020 09:02:13 +0200 Message-ID: <1596610933-32599-19-git-send-email-alain.volmat@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596610933-32599-1-git-send-email-alain.volmat@st.com> References: <1596610933-32599-1-git-send-email-alain.volmat@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.75.127.49] X-ClientProxiedBy: SFHDAG2NODE3.st.com (10.75.127.6) To SFHDAG3NODE2.st.com (10.75.127.8) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-08-05_04:2020-08-03,2020-08-05 signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Ensure that messages given to transfer_one handler can actually be handled by it. For that purpose rely on the SPI framework spi_split_transfers_maxsize function to split messages whenever necessary. Signed-off-by: Alain Volmat --- drivers/spi/spi-stm32.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c index b909afd9e99b..bd21b698af84 100644 --- a/drivers/spi/spi-stm32.c +++ b/drivers/spi/spi-stm32.c @@ -1021,6 +1021,20 @@ static int stm32_spi_prepare_msg(struct spi_master *master, spi_dev->mode & SPI_LSB_FIRST, spi_dev->mode & SPI_CS_HIGH); + /* On STM32H7, messages should not exceed a maximum size setted + * afterward via the set_number_of_data function. In order to + * ensure that, split large messages into several messages + */ + if (spi->cfg->set_number_of_data) { + int ret; + + ret = spi_split_transfers_maxsize(master, msg, + STM32H7_SPI_TSIZE_MAX, + GFP_KERNEL | GFP_DMA); + if (ret) + return ret; + } + spin_lock_irqsave(&spi->lock, flags); /* CPOL, CPHA and LSB FIRST bits have common register */ -- 2.7.4