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([2601:646:c200:1ef2:a84d:be3c:49a:e3a1]) by smtp.gmail.com with ESMTPSA id js19sm3920084pjb.33.2020.08.05.13.30.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 05 Aug 2020 13:30:35 -0700 (PDT) Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable From: Andy Lutomirski Mime-Version: 1.0 (1.0) Subject: Re: [PATCH v2] x86/cpu: Use SERIALIZE in sync_core() when available Date: Wed, 5 Aug 2020 13:30:32 -0700 Message-Id: References: <20200805191126.GA27509@ranerica-svr.sc.intel.com> Cc: Andy Lutomirski , Borislav Petkov , "H. Peter Anvin" , Borislav Petkov , Thomas Gleixner , Ingo Molnar , X86 ML , "Peter Zijlstra (Intel)" , Dave Hansen , Tony Luck , Cathy Zhang , Fenghua Yu , Kyung Min Park , "Ravi V. Shankar" , Sean Christopherson , LKML , Ricardo Neri , Dave Hansen , linux-edac In-Reply-To: <20200805191126.GA27509@ranerica-svr.sc.intel.com> To: Ricardo Neri X-Mailer: iPhone Mail (17G68) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > On Aug 5, 2020, at 12:11 PM, Ricardo Neri wrote: >=20 > =EF=BB=BFOn Wed, Aug 05, 2020 at 11:28:31AM -0700, Andy Lutomirski wrote: >>> On Wed, Aug 5, 2020 at 10:07 AM Ricardo Neri >>> wrote: >>>=20 >>> On Wed, Aug 05, 2020 at 07:08:08AM +0200, Borislav Petkov wrote: >>>> On Tue, Aug 04, 2020 at 09:58:25PM -0700, hpa@zytor.com wrote: >>>>> Because why use an alternative to jump over one instruction? >>>>>=20 >>>>> I personally would prefer to have the IRET put out of line >>>>=20 >>>> Can't yet - SERIALIZE CPUs are a minority at the moment. >>>>=20 >>>>> and have the call/jmp replaced by SERIALIZE inline. >>>>=20 >>>> Well, we could do: >>>>=20 >>>> alternative_io("... IRET bunch", __ASM_SERIALIZE, X86_FEATURE_SERI= ALIZE, ...); >>>>=20 >>>> and avoid all kinds of jumping. Alternatives get padded so there >>>> would be a couple of NOPs following when SERIALIZE gets patched in >>>> but it shouldn't be a problem. I guess one needs to look at what gcc >>>> generates... >>>=20 >>> But the IRET-TO-SELF code has instruction which modify the stack. This >>> would violate stack invariance in alternatives as enforced in commit >>> 7117f16bf460 ("objtool: Fix ORC vs alternatives"). As a result, objtool >>> gives warnings as follows: >>>=20 >>> arch/x86/kernel/alternative.o: warning: objtool: do_sync_core()+0xe: >>> alternative modifies stack >>>=20 >>> Perhaps in this specific case it does not matter as the changes in the >>> stack will be undone by IRET. However, using alternative_io would requir= e >>> adding the macro STACK_FRAME_NON_STANDARD to functions using sync_core()= . >>> IMHO, it wouldn't look good. >>>=20 >>> So maybe the best approach is to implement as you suggested using >>> static_cpu_has()? >>=20 >> I agree. Let's keep it simple. >>=20 >> Honestly, I think the right solution is to have iret_to_self() in >> actual asm and invoke it from C as needed.=20 >=20 > Do you mean anything different from what we have already [1]? If I > understand your comment correctly, we have exactly that: an > iret_to_self() asm implementation invoked from C. I meant asm as in a .S file. But the code we have is fine for this purpose, a= t least for now. >=20 > Thanks and BR, > Ricardo >=20 > [1]. https://lore.kernel.org/lkml/20200727043132.15082-4-ricardo.neri-cald= eron@linux.intel.com/ >=20 > Thanks and BR, > Ricardo