Received: by 2002:a05:6a10:a0d1:0:0:0:0 with SMTP id j17csp1557988pxa; Thu, 6 Aug 2020 10:13:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwd5hFYK4Gu1KCQTTNoelU8TCFuUd1v1Y+tCovXPDygwUVQs0jlxlaQGRN9XXHnmhwRMgtO X-Received: by 2002:a17:906:3c43:: with SMTP id i3mr5583621ejg.133.1596734017904; Thu, 06 Aug 2020 10:13:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1596734017; cv=none; d=google.com; s=arc-20160816; b=c8tQxKgSsJCpabbitmjXmvRSpot9BUyHpZumWPrmxzZt7yWqlVeiehWwzVsWvtvWZm Lzhwo6XYvHTGFHveGiW5kxpSvAp+hESX7nHfTngJDwsWEESHiZA/BB7LZ7rHi9MvQUEo W7zEHlYxjmDNpwcOZ+jGl4uZlWm6EhZdOOT056YZf/Uay3ujW77ZQG4pgmkEin04Z3/x nUCsYIKaV/pgx7s6mIygzIc8MhBPAaFRGp8vkW0aNWZeIVmexVllwRYk6Wx6UyyWL+H/ NSIKGol892td8x/sTX0bDq35YJfOSoCZ84P1YIJVJId9AnMRjzBltNhgWh5gs6R2ZHPr KjiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:user-agent:in-reply-to :content-disposition:mime-version:references:message-id:subject:cc :to:from:date; bh=TieUErr7jXEAKZP6QYPxuzpjZJBSeXZWlKQDS6A07kk=; b=MFxxzuf5bBGhHnSPtyP7Pj3eNDMXwVZe6pu4Cv9Tjd8k65MiNLCYxQRiyrYrApuZEL UvDFrkQjGlZTskX+vrO3FyfmhV9YJJimaP8U+6L43B+79sWY9J/he0eBARw6g4VTMYAb Q1eOhKcwyJORQbovAjaBqNtcD71Iu4aN+7KwcuKn1GTo25CcxotHGx//1TXLfxzTQrZq A/zAiJy9gAzUb9skXPQ5b5rDm11nhCGlLC3lmDu3WFFpRT/9GOYubc4rVOHo/7MWKQWS 4jNemZPqVXOEuyaux3icmyhTvl+z2MUuQyBzc7WqrQEgNGRe2C+ctzE4qd/EBXs1zgie Yecw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id c22si3749553edr.146.2020.08.06.10.13.15; Thu, 06 Aug 2020 10:13:37 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730388AbgHFRMk (ORCPT + 99 others); Thu, 6 Aug 2020 13:12:40 -0400 Received: from foss.arm.com ([217.140.110.172]:45656 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730159AbgHFRMf (ORCPT ); Thu, 6 Aug 2020 13:12:35 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9D8001FB; Thu, 6 Aug 2020 05:01:13 -0700 (PDT) Received: from gaia (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1D4243F99C; Thu, 6 Aug 2020 05:01:12 -0700 (PDT) Date: Thu, 6 Aug 2020 13:01:09 +0100 From: Catalin Marinas To: Sami Tolvanen Cc: Will Deacon , Zhenyu Ye , Mark Rutland , Marc Zyngier , Nick Desaulniers , Nathan Chancellor , Kees Cook , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, clang-built-linux@googlegroups.com Subject: Re: [PATCH] arm64: tlb: fix ARM64_TLB_RANGE with LLVM's integrated assembler Message-ID: <20200806120109.GD23785@gaia> References: <20200805181920.4013059-1-samitolvanen@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200805181920.4013059-1-samitolvanen@google.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Aug 05, 2020 at 11:19:20AM -0700, Sami Tolvanen wrote: > diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h > index d493174415db..66c2aab5e9cb 100644 > --- a/arch/arm64/include/asm/tlbflush.h > +++ b/arch/arm64/include/asm/tlbflush.h > @@ -16,6 +16,16 @@ > #include > #include > > +/* > + * Enable ARMv8.4-TLBI instructions with ARM64_TLB_RANGE. Note that binutils > + * doesn't support .arch_extension tlb-rmi, so use .arch armv8.4-a instead. > + */ > +#ifdef CONFIG_ARM64_TLB_RANGE > +#define __TLBI_PREAMBLE ".arch armv8.4-a\n" > +#else > +#define __TLBI_PREAMBLE > +#endif > + > /* > * Raw TLBI operations. > * > @@ -28,14 +38,16 @@ > * not. The macros handles invoking the asm with or without the > * register argument as appropriate. > */ > -#define __TLBI_0(op, arg) asm ("tlbi " #op "\n" \ > +#define __TLBI_0(op, arg) asm (__TLBI_PREAMBLE \ > + "tlbi " #op "\n" \ > ALTERNATIVE("nop\n nop", \ > "dsb ish\n tlbi " #op, \ > ARM64_WORKAROUND_REPEAT_TLBI, \ > CONFIG_ARM64_WORKAROUND_REPEAT_TLBI) \ > : : ) > > -#define __TLBI_1(op, arg) asm ("tlbi " #op ", %0\n" \ > +#define __TLBI_1(op, arg) asm (__TLBI_PREAMBLE \ > + "tlbi " #op ", %0\n" \ > ALTERNATIVE("nop\n nop", \ > "dsb ish\n tlbi " #op ", %0", \ > ARM64_WORKAROUND_REPEAT_TLBI, \ A potential problem here is that for gas (not sure about the integrated assembler), .arch overrides any other .arch. So if we end up with two preambles included in the same generated .S files in the future, it will lead to some random behaviour. Does the LLVM integrated assembler have the same behaviour on .arch overriding a prior .arch? Maybe a better solution is for all inline asm on arm64 to have a standard preamble which is the maximum supported architecture version. We can add individual .arch_extension as those are not overriding. -- Catalin