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Subject: Re: [PATCH v9 08/10] gpu: host1x: mipi: Keep MIPI clock enabled and
 mutex locked till calibration done
To:     Sowjanya Komatineni <skomatineni@nvidia.com>,
        thierry.reding@gmail.com, jonathanh@nvidia.com, frankc@nvidia.com,
        hverkuil@xs4all.nl, sakari.ailus@iki.fi, robh+dt@kernel.org,
        helen.koike@collabora.com
Cc:     gregkh@linuxfoundation.org, linux-media@vger.kernel.org,
        devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
        linux-kernel@vger.kernel.org
References: <1596740494-19306-1-git-send-email-skomatineni@nvidia.com>
 <1596740494-19306-9-git-send-email-skomatineni@nvidia.com>
From:   Dmitry Osipenko <digetx@gmail.com>
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Date:   Fri, 7 Aug 2020 05:31:30 +0300
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06.08.2020 22:01, Sowjanya Komatineni пишет:
...
> +int tegra_mipi_start_calibration(struct tegra_mipi_device *device)
>  {
>  	const struct tegra_mipi_soc *soc = device->mipi->soc;
>  	unsigned int i;
> @@ -381,12 +375,16 @@ int tegra_mipi_calibrate(struct tegra_mipi_device *device)
>  	value |= MIPI_CAL_CTRL_START;
>  	tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL);
>  
> -	mutex_unlock(&device->mipi->lock);
> -	clk_disable(device->mipi->clk);
> +	/*
> +	 * Wait for min 72uS to let calibration logic finish calibration
> +	 * sequence codes before waiting for pads idle state to apply the
> +	 * results.
> +	 */
> +	usleep_range(75, 80);

Could you please explain why the ACTIVE bit can't be polled instead of
using the fixed delay? Doesn't ACTIVE bit represents the state of the
busy FSM?