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Subject: Re: [PATCH v9 08/10] gpu: host1x: mipi: Keep MIPI clock enabled and
 mutex locked till calibration done
To:     Dmitry Osipenko <digetx@gmail.com>, <thierry.reding@gmail.com>,
        <jonathanh@nvidia.com>, <frankc@nvidia.com>, <hverkuil@xs4all.nl>,
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From:   Sowjanya Komatineni <skomatineni@nvidia.com>
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On 8/6/20 7:31 PM, Dmitry Osipenko wrote:
> 06.08.2020 22:01, Sowjanya Komatineni =D0=BF=D0=B8=D1=88=D0=B5=D1=82:
> ...
>> +int tegra_mipi_start_calibration(struct tegra_mipi_device *device)
>>   {
>>   	const struct tegra_mipi_soc *soc =3D device->mipi->soc;
>>   	unsigned int i;
>> @@ -381,12 +375,16 @@ int tegra_mipi_calibrate(struct tegra_mipi_device =
*device)
>>   	value |=3D MIPI_CAL_CTRL_START;
>>   	tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL);
>>  =20
>> -	mutex_unlock(&device->mipi->lock);
>> -	clk_disable(device->mipi->clk);
>> +	/*
>> +	 * Wait for min 72uS to let calibration logic finish calibration
>> +	 * sequence codes before waiting for pads idle state to apply the
>> +	 * results.
>> +	 */
>> +	usleep_range(75, 80);
> Could you please explain why the ACTIVE bit can't be polled instead of
> using the fixed delay? Doesn't ACTIVE bit represents the state of the
> busy FSM?

Based on internal discussion, ACTIVE bit gets cleared when all enabled=20
pads calibration is done (same time as when DONE set to 1).

Will request HW designer to look into design and confirm=C2=A0 exactly when=
=20
ACTIVE bit gets cleared.

Will get back on this.