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Subject: Re: [PATCH v9 08/10] gpu: host1x: mipi: Keep MIPI clock enabled and
 mutex locked till calibration done
From:   Sowjanya Komatineni <skomatineni@nvidia.com>
To:     Dmitry Osipenko <digetx@gmail.com>, <thierry.reding@gmail.com>,
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On 8/6/20 8:10 PM, Sowjanya Komatineni wrote:
>
> On 8/6/20 7:31 PM, Dmitry Osipenko wrote:
>> 06.08.2020 22:01, Sowjanya Komatineni =D0=BF=D0=B8=D1=88=D0=B5=D1=82:
>> ...
>>> +int tegra_mipi_start_calibration(struct tegra_mipi_device *device)
>>> =C2=A0 {
>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 const struct tegra_mipi_soc *soc =3D dev=
ice->mipi->soc;
>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 unsigned int i;
>>> @@ -381,12 +375,16 @@ int tegra_mipi_calibrate(struct=20
>>> tegra_mipi_device *device)
>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 value |=3D MIPI_CAL_CTRL_START;
>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 tegra_mipi_writel(device->mipi, value, M=
IPI_CAL_CTRL);
>>> =C2=A0 -=C2=A0=C2=A0=C2=A0 mutex_unlock(&device->mipi->lock);
>>> -=C2=A0=C2=A0=C2=A0 clk_disable(device->mipi->clk);
>>> +=C2=A0=C2=A0=C2=A0 /*
>>> +=C2=A0=C2=A0=C2=A0=C2=A0 * Wait for min 72uS to let calibration logic =
finish calibration
>>> +=C2=A0=C2=A0=C2=A0=C2=A0 * sequence codes before waiting for pads idle=
 state to apply the
>>> +=C2=A0=C2=A0=C2=A0=C2=A0 * results.
>>> +=C2=A0=C2=A0=C2=A0=C2=A0 */
>>> +=C2=A0=C2=A0=C2=A0 usleep_range(75, 80);
>> Could you please explain why the ACTIVE bit can't be polled instead of
>> using the fixed delay? Doesn't ACTIVE bit represents the state of the
>> busy FSM?
>
> Based on internal discussion, ACTIVE bit gets cleared when all enabled=20
> pads calibration is done (same time as when DONE set to 1).
>
> Will request HW designer to look into design and confirm=C2=A0 exactly wh=
en=20
> ACTIVE bit gets cleared.
>
> Will get back on this.
>
Verified with HW designer. above is correct. ACTIVE bit update happens=20
same time as DONE bit.

Active =3D !(DONE)

In case of calibration logic waiting for LP-11 where done bit does not=20
get set, ACTIVE will still be 1 and on next start trigger new=20
calibration will start

>
>