Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
Subject: Re: [PATCH v9 08/10] gpu: host1x: mipi: Keep MIPI clock enabled and
 mutex locked till calibration done
To:     Sowjanya Komatineni <skomatineni@nvidia.com>,
        thierry.reding@gmail.com, jonathanh@nvidia.com, frankc@nvidia.com,
        hverkuil@xs4all.nl, sakari.ailus@iki.fi, robh+dt@kernel.org,
        helen.koike@collabora.com
Cc:     gregkh@linuxfoundation.org, linux-media@vger.kernel.org,
        devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
        linux-kernel@vger.kernel.org
References: <1596740494-19306-1-git-send-email-skomatineni@nvidia.com>
 <1596740494-19306-9-git-send-email-skomatineni@nvidia.com>
 <f2522713-6995-d6a1-e691-a5443823056b@gmail.com>
 <7ef2a6dd-d220-ff47-e6ef-7443a1779fae@nvidia.com>
 <a0a187d3-04e9-88d9-5146-1448d4bd79e9@nvidia.com>
 <54e01160-4041-f8fa-065d-f635e8d69e2f@nvidia.com>
From:   Dmitry Osipenko <digetx@gmail.com>
Message-ID: <7c47b165-8663-87f0-bff5-37036d472fb9@gmail.com>
Date:   Fri, 7 Aug 2020 07:01:36 +0300
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101
 Thunderbird/68.10.0
MIME-Version: 1.0
In-Reply-To: <54e01160-4041-f8fa-065d-f635e8d69e2f@nvidia.com>
Content-Type: text/plain; charset=utf-8
Content-Language: en-US
Content-Transfer-Encoding: 8bit
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

07.08.2020 06:18, Sowjanya Komatineni пишет:
> 
> On 8/6/20 8:14 PM, Sowjanya Komatineni wrote:
>>
>> On 8/6/20 8:10 PM, Sowjanya Komatineni wrote:
>>>
>>> On 8/6/20 7:31 PM, Dmitry Osipenko wrote:
>>>> 06.08.2020 22:01, Sowjanya Komatineni пишет:
>>>> ...
>>>>> +int tegra_mipi_start_calibration(struct tegra_mipi_device *device)
>>>>>   {
>>>>>       const struct tegra_mipi_soc *soc = device->mipi->soc;
>>>>>       unsigned int i;
>>>>> @@ -381,12 +375,16 @@ int tegra_mipi_calibrate(struct
>>>>> tegra_mipi_device *device)
>>>>>       value |= MIPI_CAL_CTRL_START;
>>>>>       tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL);
>>>>>   -    mutex_unlock(&device->mipi->lock);
>>>>> -    clk_disable(device->mipi->clk);
>>>>> +    /*
>>>>> +     * Wait for min 72uS to let calibration logic finish calibration
>>>>> +     * sequence codes before waiting for pads idle state to apply the
>>>>> +     * results.
>>>>> +     */
>>>>> +    usleep_range(75, 80);
>>>> Could you please explain why the ACTIVE bit can't be polled instead of
>>>> using the fixed delay? Doesn't ACTIVE bit represents the state of the
>>>> busy FSM?
>>>
>>> Based on internal discussion, ACTIVE bit gets cleared when all
>>> enabled pads calibration is done (same time as when DONE set to 1).
>>>
>>> Will request HW designer to look into design and confirm exactly when
>>> ACTIVE bit gets cleared.
>>>
>>> Will get back on this.
>>>
>> Verified with HW designer. above is correct. ACTIVE bit update happens
>> same time as DONE bit.
>>
>> Active = !(DONE)
>>
>> In case of calibration logic waiting for LP-11 where done bit does not
>> get set, ACTIVE will still be 1 and on next start trigger new
>> calibration will start
>>
> Based on internal design check from designer, as long as its in waiting
> for LP-11 stage, next calibration request can be triggered again but
> ACTIVE bit we will see it at 1. So we should check for DONE bits to
> confirm if calibration is done or not.
> 
> To start next calibration, it can take effect as long as its in wait for
> LP-11 mode.

I meant the start_calibration() will poll the ACTIVE bit (calibration
busy), while the finish_calibration() will poll the DONE bit
(calibration applied).