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From:   Venkateshwar Rao Gannavarapu 
        <venkateshwar.rao.gannavarapu@xilinx.com>
To:     hyun.kwon@xilinx.com, laurent.pinchart@ideasonboard.com,
        dri-devel@lists.freedesktop.org
Cc:     airlied@linux.ie, daniel@ffwll.ch, linux-kernel@vger.kernel.org,
        sandipk@xilinx.com, vgannava@xilinx.com,
        Venkateshwar Rao Gannavarapu 
        <venkateshwar.rao.gannavarapu@xilinx.com>
Subject: [RFC PATCH V2 1/2] dt-bindings: display: xlnx: dsi: This add a DT binding for Xilinx DSI TX subsystem.
Date:   Tue, 11 Aug 2020 06:16:16 +0530
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The Xilinx MIPI DSI (Display Serial Interface) Transmitter subsystem
implements the Mobile Industry Processor Interface (MIPI) based display
interface. It supports the interface with programmable logic (FPGA).

Signed-off-by: Venkateshwar Rao Gannavarapu <venkateshwar.rao.gannavarapu@x=
ilinx.com>
---
 .../devicetree/bindings/display/xlnx/xlnx,dsi.yaml | 147 +++++++++++++++++=
++++
 1 file changed, 147 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/xlnx/xlnx,dsi=
.yaml

diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.yaml b=
/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.yaml
new file mode 100644
index 0000000..73da0d8
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.yaml
@@ -0,0 +1,147 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/xlnx/xlnx,dsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Programmable DSI-TX Subsystem
+
+description: |
+  The programmable MIPI DSI controller of Xilinx implements display pipeli=
ne
+  based on DSI v1.3 specification. The subsystem includes multiple functio=
nal
+  blocks as below
+
+  +---------------+                +--------------------------------------=
---------+
+  |               |                |                      +---------------=
---+     |
+  |               |                |         v----------->+AXI CROSBAR    =
   |XXX  |
+  |FRAME BUFFER   | AXI STREAM     |         |            |               =
   X   X |
+  |(DMA)          |       +------->+    +------------+    +---------------=
---+  XX |
+  |               +<------+        |    |MIPI        |                    =
      X  |
+  |               |                |    |DSI-TX      |                    =
      X  |
+  |               |                |    |Controller  |             +------=
------+  |
+  |               |                |    |            +------------->D-PHY =
      |  |
+  +---------------+                |    |            |             |      =
      |  |
+                  S_AXIS_ACLK      |    +-------------<------------+      =
      |  |
+                 +---------------->+                               |      =
      |  |
+                                   |                               |      =
      |  |
+                  DPHY_CLK_200M    |                               |      =
      |  |
+                 +---------------->+                               |      =
      |  |
+                 +                 |                               +------=
------+  |
+                                   |                                      =
         |
+                                   | MIPI DSI TX SUBSYSTEM                =
         |
+                                   +--------------------------------------=
---------+
+
+  The DSI TX controller consists of multiple layers such as lane managemen=
t layer,
+  low-level protocol and pixel-to-byte conversion. The DSI TX controller c=
ore
+  receives stream of image data through an input stream interface. The sub=
system
+  driver supports upto 4 lane support and generates PPI trasfers towards D=
PHY
+  with continuous clock. It supports Burst, non-burst modes and command mo=
des.
+
+maintainers:
+  - Venkateshwar Rao Gannavarapu <venkateshwar.rao.gannavarapu@xilinx.com>
+
+properties:
+  compatible:
+    const: xlnx,dsi-1.0
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    description: List of clock specifiers
+    items:
+      - description: AXI Lite clock
+      - description: Video DPHY clock
+
+  clock-names:
+    items:
+      - const: s_axis_aclk
+      - const: dphy_clk_200M
+
+  xlnx,dsi-num-lanes:
+    description: Maximum number of lanes that IP configured with.
+           possible values are 1, 2, 4.
+
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/uint32
+      - enum: [1, 2, 4]
+
+  xlnx,dsi-data-type:
+    description: MIPI DSI pixel format.
+           possible values are 0, 1, 2, 3.
+
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/uint32
+      - enum: [0, 1, 2, 3]
+
+  xlnx,dsi-cmd-mode:
+    description: denotes command mode support
+
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/uint32
+      - enum: [0, 1]
+
+  ports:
+    type: object
+
+    properties:
+      port@0:
+        type: object
+        description: |
+          output / source port node, endpoint describing modules
+          connected the DSI TX subsystem
+
+        properties:
+          reg:
+            const: 0
+
+          endpoint:
+            type: object
+
+            properties:
+
+              remote-endpoint: true
+
+            required:
+              - remote-endpoint
+
+            additionalProperties: false
+
+        additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - xlnx,dsi-num-lanes
+  - xlnx,dsi-data-type
+  - xlnx,dsi-cmd-mode
+  - ports
+
+additionalProperties: false
+
+examples:
+ -  |
+    mipi_dsi_tx_subsystem@80000000 {
+      compatible =3D "xlnx,dsi-1.0";
+      reg =3D <0x0 0x80000000 0x0 0x10000>;
+      clocks =3D <&misc_clk_0>, <&misc_clk_1>;
+      clock-names =3D "s_axis_aclk", "dphy_clk_200M";
+      xlnx,dsi-num-lanes =3D <4>;
+      xlnx,dsi-data-type =3D <1>;
+      xlnx,dsi-cmd-mode =3D <0>;
+      ports {
+          #address-cells =3D <1>;
+          #size-cells =3D <0>;
+
+          port@0 {
+              reg =3D <0x0>;
+              dsi_tx_out: endpoint {
+                   remote-endpoint =3D <&panel_in>;
+              };
+          };
+      };
+    };
+
+...
--
1.8.3.1

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