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Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 11 Aug 2020 14:50:45 +0800 Message-ID: <1597128646.20627.17.camel@mtksdaap41> Subject: Re: [PATCH v2 3/5] clk: mediatek: Fix asymmetrical PLL enable and disable control From: Weiyi Lu To: Nicolas Boichat CC: Matthias Brugger , Rob Herring , Stephen Boyd , James Liao , linux-arm Mailing List , lkml , "moderated list:ARM/Mediatek SoC support" , , srv_heupstream , Wendell Lin Date: Tue, 11 Aug 2020 14:50:46 +0800 In-Reply-To: References: <1596012277-8448-1-git-send-email-weiyi.lu@mediatek.com> <1596012277-8448-4-git-send-email-weiyi.lu@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: base64 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org T24gV2VkLCAyMDIwLTA3LTI5IGF0IDE4OjUxICswODAwLCBOaWNvbGFzIEJvaWNoYXQgd3JvdGU6 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