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        <noltari@gmail.com>
Subject: [PATCH 06/14] mips: bmips: add BCM6362 irq definitions
Date:   Wed, 12 Aug 2020 08:31:21 +0200
Message-Id: <20200812063129.361862-7-noltari@gmail.com>
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Add header with BCM6362 definitions in order to be able to include it from
device tree files.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
 .../bcm6362-interrupt-controller.h            | 71 +++++++++++++++++++
 1 file changed, 71 insertions(+)
 create mode 100644 include/dt-bindings/interrupt-controller/bcm6362-interrupt-controller.h

diff --git a/include/dt-bindings/interrupt-controller/bcm6362-interrupt-controller.h b/include/dt-bindings/interrupt-controller/bcm6362-interrupt-controller.h
new file mode 100644
index 000000000000..7a13046f0d81
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/bcm6362-interrupt-controller.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6362_H
+#define __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6362_H
+
+#define BCM6362_IRQ_TIMER		0
+#define BCM6362_IRQ_RING_OSC		1
+#define BCM6362_IRQ_LSSPI		2
+#define BCM6362_IRQ_UART0		3
+#define BCM6362_IRQ_UART1		4
+#define BCM6362_IRQ_HSSPI		5
+#define BCM6362_IRQ_WLAN_GPIO		6
+#define BCM6362_IRQ_WLAN		7
+#define BCM6362_IRQ_IPSEC		8
+#define BCM6362_IRQ_OHCI		9
+#define BCM6362_IRQ_EHCI		10
+#define BCM6362_IRQ_USBS		11
+#define BCM6362_IRQ_NAND		12
+#define BCM6362_IRQ_PCM			13
+#define BCM6362_IRQ_EPHY		14
+#define BCM6362_IRQ_DF			15
+#define BCM6362_IRQ_EPHY_EN0		16
+#define BCM6362_IRQ_EPHY_EN1		17
+#define BCM6362_IRQ_EPHY_EN2		18
+#define BCM6362_IRQ_EPHY_EN3		19
+#define BCM6362_IRQ_USB_CTL_RX_DMA	20
+#define BCM6362_IRQ_USB_CTL_TX_DMA	21
+#define BCM6362_IRQ_USB_BULK_RX_DMA	22
+#define BCM6362_IRQ_USB_BULK_TX_DMA	23
+#define BCM6362_IRQ_USB_ISO_RX_DMA	24
+#define BCM6362_IRQ_USB_ISO_TX_DMA	25
+#define BCM6362_IRQ_IPSEC_DMA0		26
+#define BCM6362_IRQ_IPSEC_DMA1		27
+#define BCM6362_IRQ_XDSL		28
+#define BCM6362_IRQ_FAP			29
+#define BCM6362_IRQ_PCIE_RC		30
+#define BCM6362_IRQ_PCIE_EP		31
+#define BCM6362_IRQ_ENETSW_RX_DMA0	32
+#define BCM6362_IRQ_ENETSW_RX_DMA1	33
+#define BCM6362_IRQ_ENETSW_RX_DMA2	34
+#define BCM6362_IRQ_ENETSW_RX_DMA3	35
+#define BCM6362_IRQ_PCM_DMA0		36
+#define BCM6362_IRQ_PCM_DMA1		37
+#define BCM6362_IRQ_DECT0		38
+#define BCM6362_IRQ_DECT1		39
+#define BCM6362_IRQ_EXT0		40
+#define BCM6362_IRQ_EXT1		41
+#define BCM6362_IRQ_EXT2		42
+#define BCM6362_IRQ_EXT3		43
+#define BCM6362_IRQ_ATM_DMA0		44
+#define BCM6362_IRQ_ATM_DMA1		45
+#define BCM6362_IRQ_ATM_DMA2		46
+#define BCM6362_IRQ_ATM_DMA3		47
+#define BCM6362_IRQ_ATM_DMA4		48
+#define BCM6362_IRQ_ATM_DMA5		49
+#define BCM6362_IRQ_ATM_DMA6		50
+#define BCM6362_IRQ_ATM_DMA7		51
+#define BCM6362_IRQ_ATM_DMA8		52
+#define BCM6362_IRQ_ATM_DMA9		53
+#define BCM6362_IRQ_ATM_DMA10		54
+#define BCM6362_IRQ_ATM_DMA11		55
+#define BCM6362_IRQ_ATM_DMA12		56
+#define BCM6362_IRQ_ATM_DMA13		57
+#define BCM6362_IRQ_ATM_DMA14		58
+#define BCM6362_IRQ_ATM_DMA15		59
+#define BCM6362_IRQ_ATM_DMA16		60
+#define BCM6362_IRQ_ATM_DMA17		61
+#define BCM6362_IRQ_ATM_DMA18		62		
+#define BCM6362_IRQ_ATM_DMA19		63
+
+#endif /* __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6362_H */
-- 
2.28.0