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From:   Damien Le Moal <Damien.LeMoal@wdc.com>
To:     Qiu Wenbo <qiuwenbo@phytium.com.cn>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>
CC:     Anup Patel <anup@brainfault.org>,
        Atish Patra <atishp@atishpatra.org>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Anup Patel <Anup.Patel@wdc.com>,
        Atish Patra <Atish.Patra@wdc.com>,
        Greentime Hu <greentime.hu@sifive.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2] riscv: Setup exception vector for nommu platform
Thread-Topic: [PATCH v2] riscv: Setup exception vector for nommu platform
Thread-Index: AQHWcSODcO8pwfBnAUaNkuIfFTKGFA==
Date:   Thu, 13 Aug 2020 05:44:23 +0000
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References: <20200813033807.19556-1-qiuwenbo@phytium.com.cn>
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On 2020/08/13 12:40, Qiu Wenbo wrote:=0A=
> Exception vector is missing on nommu platform and that is an issue.=0A=
> This patch is tested in Sipeed Maix Bit Dev Board.=0A=
> =0A=
> Fixes: 79b1feba5455 ("RISC-V: Setup exception vector early")=0A=
> Suggested-by: Anup Patel <anup@brainfault.org>=0A=
> Suggested-by: Atish Patra <atishp@atishpatra.org>=0A=
> Signed-off-by: Qiu Wenbo <qiuwenbo@phytium.com.cn>=0A=
=0A=
Please add a cc stable #5.8 tag. Kendryte support is in 5.8 stable.=0A=
=0A=
> ---=0A=
>  arch/riscv/kernel/head.S | 25 +++++++++++++++++--------=0A=
>  1 file changed, 17 insertions(+), 8 deletions(-)=0A=
> =0A=
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S=0A=
> index d0c5c316e9bb..0a4e81b8dc79 100644=0A=
> --- a/arch/riscv/kernel/head.S=0A=
> +++ b/arch/riscv/kernel/head.S=0A=
> @@ -77,16 +77,10 @@ relocate:=0A=
>  	csrw CSR_SATP, a0=0A=
>  .align 2=0A=
>  1:=0A=
> -	/* Set trap vector to exception handler */=0A=
> -	la a0, handle_exception=0A=
> +	/* Set trap vector to spin forever to help debug */=0A=
> +	la a0, .Lsecondary_park=0A=
>  	csrw CSR_TVEC, a0=0A=
>  =0A=
> -	/*=0A=
> -	 * Set sup0 scratch register to 0, indicating to exception vector that=
=0A=
> -	 * we are presently executing in kernel.=0A=
> -	 */=0A=
> -	csrw CSR_SCRATCH, zero=0A=
> -=0A=
>  	/* Reload the global pointer */=0A=
>  .option push=0A=
>  .option norelax=0A=
> @@ -144,9 +138,23 @@ secondary_start_common:=0A=
>  	la a0, swapper_pg_dir=0A=
>  	call relocate=0A=
>  #endif=0A=
> +	call setup_trap_vector=0A=
>  	tail smp_callin=0A=
>  #endif /* CONFIG_SMP */=0A=
>  =0A=
> +.align 2=0A=
> +setup_trap_vector:=0A=
> +	/* Set trap vector to exception handler */=0A=
> +	la a0, handle_exception=0A=
> +	csrw CSR_TVEC, a0=0A=
> +=0A=
> +	/*=0A=
> +	 * Set sup0 scratch register to 0, indicating to exception vector that=
=0A=
> +	 * we are presently executing in kernel.=0A=
> +	 */=0A=
> +	csrw CSR_SCRATCH, zero=0A=
> +	ret=0A=
> +=0A=
>  .Lsecondary_park:=0A=
>  	/* We lack SMP support or have too many harts, so park this hart */=0A=
>  	wfi=0A=
> @@ -240,6 +248,7 @@ clear_bss_done:=0A=
>  	call relocate=0A=
>  #endif /* CONFIG_MMU */=0A=
>  =0A=
> +	call setup_trap_vector=0A=
>  	/* Restore C environment */=0A=
>  	la tp, init_task=0A=
>  	sw zero, TASK_TI_CPU(tp)=0A=
> =0A=
=0A=
=0A=
-- =0A=
Damien Le Moal=0A=
Western Digital Research=0A=