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[83.6.170.79]) by smtp.googlemail.com with ESMTPSA id e8sm6087974edy.68.2020.08.14.08.22.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Aug 2020 08:22:04 -0700 (PDT) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: Konrad Dybcio , Ulf Hansson , Rob Herring , Andy Gross , Bjorn Andersson , Adrian Hunter , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH 1/2] [-next] mmc: host: msm: Add optional full power cycle property. Date: Fri, 14 Aug 2020 17:21:59 +0200 Message-Id: <20200814152201.254010-1-konradybcio@gmail.com> X-Mailer: git-send-email 2.28.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On some eMMCs (at least the ones used on Sony msm8994 boards) enabling full power cycle is required to prevent permanent damage to the flash memory, whereas on others it results in better performance. Signed-off-by: Konrad Dybcio --- Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 4 ++++ drivers/mmc/host/sdhci-msm.c | 6 ++++++ 2 files changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt index 3b602fd6180b..939c8df2a25c 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt @@ -54,6 +54,10 @@ Required properties: - qcom,dll-config: Chipset and Platform specific value. Use this field to specify the DLL_CONFIG register value as per Hardware Programming Guide. +- qcom,full-pwr-cycle: Enable full power cycle CAP2. This is required for optimal + performance on some eMMCs, whereas others need it to prevent permanent + damage to the flash memory. + Optional Properties: * Following bus parameters are required for interconnect bandwidth scaling: - interconnects: Pairs of phandles and interconnect provider specifier diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 5a33389037cd..8d5c65e13dca 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -2242,6 +2242,12 @@ static int sdhci_msm_probe(struct platform_device *pdev) msm_host->saved_tuning_phase = INVALID_TUNING_PHASE; + if (of_find_property(pdev->dev.of_node, "qcom,full-pwr-cycle", NULL)) + msm_host->mmc->caps2 |= MMC_CAP2_FULL_PWR_CYCLE; + + else + dev_info(&pdev->dev, "MMC full power cycle is not enabled. This might result in subpar performance or permanent damage on some devices.\n"); + /* Setup SDCC bus voter clock. */ msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus"); if (!IS_ERR(msm_host->bus_clk)) { -- 2.28.0