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From:   Rob Clark <robdclark@gmail.com>
Date:   Sat, 15 Aug 2020 13:20:35 -0700
Message-ID: <CAF6AEGtcfXodN1_HSdTcH402FdwTk15Nt6p3F=QYeSRhTc+hqw@mail.gmail.com>
Subject: Re: [PATCH v10 3/5] drm/msm/dp: add support for DP PLL driver
To:     Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc:     Tanmay Shah <tanmay@codeaurora.org>,
        Stephen Boyd <swboyd@chromium.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>,
        linux-arm-msm <linux-arm-msm@vger.kernel.org>,
        dri-devel <dri-devel@lists.freedesktop.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        freedreno <freedreno@lists.freedesktop.org>,
        Sean Paul <seanpaul@chromium.org>,
        Daniel Vetter <daniel@ffwll.ch>,
        David Airlie <airlied@linux.ie>, aravindh@codeaurora.org,
        Abhinav Kumar <abhinavk@codeaurora.org>, khsieh@codeaurora.org,
        Chandan Uddaraju <chandanu@codeaurora.org>,
        Vara Reddy <varar@codeaurora.org>
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On Fri, Aug 14, 2020 at 10:05 AM Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
>
>
> On 12/08/2020 07:42, Tanmay Shah wrote:
>  > From: Chandan Uddaraju <chandanu@codeaurora.org>
>  >
>  > Add the needed DP PLL specific files to support
>  > display port interface on msm targets.
>
> [skipped]
>
>  > diff --git a/drivers/gpu/drm/msm/dp/dp_pll_private.h
> b/drivers/gpu/drm/msm/dp/dp_pll_private.h
>  > new file mode 100644
>  > index 000000000000..475ba6ed59ab
>  > --- /dev/null
>  > +++ b/drivers/gpu/drm/msm/dp/dp_pll_private.h
>  > @@ -0,0 +1,98 @@
>  > +/* SPDX-License-Identifier: GPL-2.0-only */
>  > +/*
>  > + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
>  > + */
>  > +
>  > +#ifndef __DP_PLL_10NM_H
>  > +#define __DP_PLL_10NM_H
>  > +
>  > +#include "dp_pll.h"
>  > +#include "dp_reg.h"
>  > +
>  > +#define DP_VCO_HSCLK_RATE_1620MHZDIV1000    1620000UL
>  > +#define DP_VCO_HSCLK_RATE_2700MHZDIV1000    2700000UL
>  > +#define DP_VCO_HSCLK_RATE_5400MHZDIV1000    5400000UL
>  > +#define DP_VCO_HSCLK_RATE_8100MHZDIV1000    8100000UL
>  > +
>  > +#define NUM_DP_CLOCKS_MAX            6
>  > +
>  > +#define DP_PHY_PLL_POLL_SLEEP_US        500
>  > +#define DP_PHY_PLL_POLL_TIMEOUT_US        10000
>  > +
>  > +#define DP_VCO_RATE_8100MHZDIV1000        8100000UL
>  > +#define DP_VCO_RATE_9720MHZDIV1000        9720000UL
>  > +#define DP_VCO_RATE_10800MHZDIV1000        10800000UL
>  > +
>  > +struct dp_pll_vco_clk {
>  > +    struct clk_hw hw;
>  > +    unsigned long    rate;        /* current vco rate */
>  > +    u64        min_rate;    /* min vco rate */
>  > +    u64        max_rate;    /* max vco rate */
>  > +    void        *priv;
>  > +};
>  > +
>  > +struct dp_pll_db {
>
> This struct should probably go into dp_pll_10nm.c. dp_pll_7nm.c, for
> example, will use slightly different structure.

Note that sboyd has a WIP series to move all of the pll code out to a
phy driver.  If there is work already happening on 7nm support, it
might be better to go with the separate phy driver approach?  I'm
still a bit undecided about whether to land the dp code initially with
the pll stuff in drm, and then continue refactoring to move to
separate phy driver upstream, or to strip out the pll code from the
beginning.  If you/someone is working on 7nm support, then feedback
about which approach is easier is welcome.

https://lore.kernel.org/dri-devel/20200611091919.108018-1-swboyd@chromium.org/

BR,
-R