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Date:   Sun, 16 Aug 2020 19:18:13 +0200 (CEST)
From:   Cameron Nemo <cnemo@tutanota.com>
To:     Devicetree <devicetree@vger.kernel.org>,
        Linux Arm Kernel <linux-arm-kernel@lists.infradead.org>,
        Linux Rockchip <linux-rockchip@lists.infradead.org>,
        Linux Kernel <linux-kernel@vger.kernel.org>,
        Linux Usb <linux-usb@vger.kernel.org>
Cc:     Robh+dt <robh+dt@kernel.org>, Heiko <heiko@sntech.de>,
        Balbi <balbi@kernel.org>, Gregkh <gregkh@linuxfoundation.org>
Message-ID: <MEsGppx--3-2@tutanota.com>
In-Reply-To: <MEsGWB_--3-2@tutanota.com>
References: <MEsGWB_--3-2@tutanota.com>
Subject: [PATCH 2/3] arm64: dts: rockchip: rk3328 usb3 controller node
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Sender: linux-kernel-owner@vger.kernel.org
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RK3328 SoCs have one USB 3.0 OTG controller which uses DWC_USB3
core's general architecture. It can act as static xHCI host
controller, static device controller, USB 3.0/2.0 OTG basing
on ID of USB3.0 PHY.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Cameron Nemo <cnemo@tutanota.com>
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 27 ++++++++++++++++++++++++
1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts=
/rockchip/rk3328.dtsi
index bbdb19a3e85d..27e86bf06d3e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -983,6 +983,33 @@ usb_host0_ohci: usb@ff5d0000 {
status =3D "disabled";
};

+=09usbdrd3: usb@ff600000 {
+=09=09compatible =3D "rockchip,rk3328-dwc3";
+=09=09clocks =3D <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
+=09=09=09 <&cru ACLK_USB3OTG>;
+=09=09clock-names =3D "ref_clk", "suspend_clk",
+=09=09=09=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "bus_clk";
+=09=09#address-cells =3D <2>;
+=09=09#size-cells =3D <2>;
+=09=09ranges;
+=09=09status =3D "disabled";
+
+=09=09usbdrd_dwc3: dwc3@ff600000 {
+=09=09=09compatible =3D "snps,dwc3";
+=09=09=09reg =3D <0x0 0xff600000 0x0 0x100000>;
+=09=09=09interrupts =3D <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+=09=09=09dr_mode =3D "otg";
+=09=09=09phy_type =3D "utmi_wide";
+=09=09=09snps,dis_enblslpm_quirk;
+=09=09=09snps,dis-u2-freeclk-exists-quirk;
+=09=09=09snps,dis_u2_susphy_quirk;
+=09=09=09snps,dis_u3_susphy_quirk;
+=09=09=09snps,dis-del-phy-power-chg-quirk;
+=09=09=09snps,dis-tx-ipgap-linecheck-quirk;
+=09=09=09status =3D "disabled";
+=09=09};
+=09};
+
gic: interrupt-controller@ff811000 {
compatible =3D "arm,gic-400";
#interrupt-cells =3D <3>;
--
2.28.0