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x-ms-exchange-antispam-messagedata: KDVM51Js5x3vEHG6C4vFaq/H9LUycw8EUZFkKQSSJtwo9ZSg9gB/wW1cjxYBnAz3wqQNTLn5owE7wZVW5THM/WQGLyuZVWBmywu3KfBX0SvgLUSl0sv2pxoJeo2yl13drwu4xhE8g1PiaCsCeXs79Bbp/vvdYn5hT6vDQZtWo+v7oNUWN8zzEk+/D/aF5STBoPqydqfLhPL6ylFvJn2C+AhLt8eRgoiGTqBIx4A8X4u11zi+VXjV1TBS/uQpUQpkXO8/xzIGLR8cpBMLwg1zoJiyA+PTzyAyBn98Sj3Gq8jYFGrafzsx3opUnd9PIRVDRiGvCGMMpbW74TDrDY0Qwuv2Mw8JIKSdCV+9xMxgFPstOw7TGhVzsVZULI8mXTuXSoV7rpeb0QVAbwaAh78ZY/wCMJesQu4Cxw/ycobgSz+KgGtFkeUF/a8KIovtpb2jivHz+d14mimaLVoVtB791pa2SLdRccjz8n6Wj//f0lCfe7Ozvwz2o2c4NoApbr8J6xjZbGx3EDYdJoCDetOgC+XFMUDIw9qThHWpl6yh4jvwpN/yCXzkp0PrwM0HjDzhieW2hmwiC2CrnTZdL935+SrXunYv9kRhp5BhQBWPu9tubOQtsaeRhlEMUt4r3aLjFBNPQKblxYn/9XMH2jkzgw== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AM8PR04MB7315.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: e69c08ef-fc9e-4211-0ea5-08d8427ee382 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Aug 2020 07:26:42.2551 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: OrLWmIBEcqgphDYzrpH72pO+qigK1AKv9jom+g8vjKZtq/rrU7lkHEGcwyG3SYSp7S30qU5hAxBO7NYqLSA1Rw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB5858 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Shawn Guo Sent: Monday, August 17, 2020 3:17 PM > On Sun, Jul 12, 2020 at 08:25:07PM -0400, Sven Van Asbroeck wrote: > > On the imx6qp QuadPlus, the h/w designers have improved enet clocking. > > > > This patchset extends the clock tree to reflect the situation on QuadPl= us. > > > > This allows board designers to choose the enet clocking method by > > making simple clocktree changes in the devicetree. > > > > Default setting: external routing of enet_ref from pad to pad. > > > > Example, change the default to enet_ref @ 125MHz clock routed internall= y: > > > > &fec { > > assigned-clocks =3D <&clks IMX6QDL_CLK_ENET_PTP>, > > <&clks IMX6QDL_CLK_ENET_REF>; > > assigned-clock-parents =3D <&clks IMX6QDL_CLK_ENET_REF>; > > assigned-clock-rates =3D <0>, <125000000>; }; > > > > To: Shawn Guo > > To: Sascha Hauer > > Cc: Pengutronix Kernel Team > > Cc: Fabio Estevam > > Cc: NXP Linux Team > > Cc: linux-kernel@vger.kernel.org > > Cc: linux-arm-kernel@lists.infradead.org > > Cc: linux-clk@vger.kernel.org > > > > Sven Van Asbroeck (5): > > ARM: mach-imx6q: do not select enet PTP clock source on QuadPlus > > clk: imx: add simple regmap-backed clock mux > > dt-bindings: imx6qdl-clock: add QuadPlus enet clocks > > clk: imx6q: support improved enet clocking on QuadPlus > > ARM: dts: imx6qp: support improved enet clocking on QuadPlus >=20 > Hi Fugang, >=20 > Can you take a look at the series? >=20 > Shawn In fact, Sven already sent the patch list to me in private for review due to miss cc to me. We discussed the series for long time and suppose Sven will send v2 patch set. Regards, Fugang