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[23.128.96.18]) by mx.google.com with ESMTP id q22si12517106edr.317.2020.08.17.20.29.48; Mon, 17 Aug 2020 20:30:12 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726568AbgHRD22 (ORCPT + 99 others); Mon, 17 Aug 2020 23:28:28 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:9825 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726357AbgHRD22 (ORCPT ); Mon, 17 Aug 2020 23:28:28 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 5E320A170C129F5B98F0; Tue, 18 Aug 2020 11:28:25 +0800 (CST) Received: from DESKTOP-5IS4806.china.huawei.com (10.174.187.22) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Tue, 18 Aug 2020 11:28:18 +0800 From: Keqian Zhu To: , , , CC: Marc Zyngier , Steven Price , "Andrew Jones" , Catalin Marinas , "Will Deacon" , James Morse , Suzuki K Poulose , , Keqian Zhu Subject: [PATCH v2 2/2] clocksource: arm_arch_timer: Correct fault programming of CNTKCTL_EL1.EVNTI Date: Tue, 18 Aug 2020 11:28:14 +0800 Message-ID: <20200818032814.15968-3-zhukeqian1@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20200818032814.15968-1-zhukeqian1@huawei.com> References: <20200818032814.15968-1-zhukeqian1@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.174.187.22] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ARM virtual counter supports event stream, it can only trigger an event when the trigger bit (the value of CNTKCTL_EL1.EVNTI) of CNTVCT_EL0 changes, so the actual period of event stream is 2^(cntkctl_evnti + 1). For example, when the trigger bit is 0, then virtual counter trigger an event for every two cycles. Fixes: 037f637767a8 ("drivers: clocksource: add support for ARM architected timer event stream") Suggested-by: Marc Zyngier Signed-off-by: Keqian Zhu --- drivers/clocksource/arm_arch_timer.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 777d38c..e3b2ee0 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -824,10 +824,14 @@ static void arch_timer_configure_evtstream(void) { int evt_stream_div, pos; - /* Find the closest power of two to the divisor */ - evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ; + /* + * Find the closest power of two to the divisor. As the event + * stream can at most be generated at half the frequency of the + * counter, use half the frequency when computing the divider. + */ + evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ / 2; pos = fls(evt_stream_div); - if (pos > 1 && !(evt_stream_div & (1 << (pos - 2)))) + if ((pos == 1) || (pos > 1 && !(evt_stream_div & (1 << (pos - 2))))) pos--; /* enable event stream */ arch_timer_evtstrm_enable(min(pos, 15)); -- 1.8.3.1