Date: Fri, 19 May 2006 13:23:47 +0300
From: Matti Aarnio <matti.aarnio@zmailer.org>
To: moreau francis <francis_moreau2000@yahoo.fr>
Cc: linux-kernel@vger.kernel.org
Subject: Re: [I2C] question on adapter design
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On Fri, May 19, 2006 at 08:42:45AM +0000, moreau francis wrote:
> I'm about writing a I2C bus adapter driver and wondering if it worth
> to use interrupt for transfering data on the bus or just polling is
> good enough ?
> 
> My hardware has a 8 bytes fifo for both Tx/Rx. It can generates
> an interrupt when Tx fifo is empty and Rx fifo is not empty, 
> actually like any UARTs. My CPU speed is 96 Mhz.

The I?C (TM Philips) -bus runs at 100 kHz or (high-speed one) at 400 kHz.
An eight bit byte goes thru it in 80 or 20 microseconds depending on used
speed.  If your interrupt processing considers it as medium level
priority and fills the Tx fifo with as much as is available (most I?C TX
sequences do fit inside the 8 byte fifo) and collects as much data as is
available in the Rx fifo, you should be well set.

Most notable detail there is, that you do have those (for I?C) huge FIFOs.
Another thing is (I haven't verified this) that I?C master controls the
bus clock, and can stop it temporarily, when Tx FIFO is empty, or Rx FIFO
is full.

> Thanks for your advices
> Francis

/Matti Aarnio
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