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[166.177.185.175]) by smtp.gmail.com with ESMTPSA id s56sm25374308qtk.72.2020.08.19.08.04.03 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 Aug 2020 08:04:03 -0700 (PDT) Date: Wed, 19 Aug 2020 11:03:59 -0400 From: Sean Paul To: Lyude Paul Cc: nouveau@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Thomas Zimmermann , David Airlie , Lucas De Marchi , open list , Gwan-gyeong Mun , Manasi Navare , Uma Shankar , Rodrigo Vivi , =?iso-8859-1?Q?Jos=E9?= Roberto de Souza , Wambui Karuga Subject: Re: [RFC 09/20] drm/i915/dp: Extract drm_dp_has_mst() Message-ID: <20200819150359.GA46474@art_vandelay> References: <20200811200457.134743-1-lyude@redhat.com> <20200811200457.134743-10-lyude@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200811200457.134743-10-lyude@redhat.com> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Aug 11, 2020 at 04:04:46PM -0400, Lyude Paul wrote: > Just a tiny drive-by cleanup, we can consolidate i915's code for > checking for MST support into a helper to be shared across drivers. > Reviewed-by: Sean Paul > Signed-off-by: Lyude Paul > --- > drivers/gpu/drm/i915/display/intel_dp.c | 18 ++---------------- > include/drm/drm_dp_mst_helper.h | 22 ++++++++++++++++++++++ > 2 files changed, 24 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 79c27f91f42c0..1e29d3a012856 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -4699,20 +4699,6 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) > return true; > } > > -static bool > -intel_dp_sink_can_mst(struct intel_dp *intel_dp) > -{ > - u8 mstm_cap; > - > - if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) > - return false; > - > - if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1) > - return false; > - > - return mstm_cap & DP_MST_CAP; > -} > - > static bool > intel_dp_can_mst(struct intel_dp *intel_dp) > { > @@ -4720,7 +4706,7 @@ intel_dp_can_mst(struct intel_dp *intel_dp) > > return i915->params.enable_dp_mst && > intel_dp->can_mst && > - intel_dp_sink_can_mst(intel_dp); > + drm_dp_has_mst(&intel_dp->aux, intel_dp->dpcd); > } > > static void > @@ -4729,7 +4715,7 @@ intel_dp_configure_mst(struct intel_dp *intel_dp) > struct drm_i915_private *i915 = dp_to_i915(intel_dp); > struct intel_encoder *encoder = > &dp_to_dig_port(intel_dp)->base; > - bool sink_can_mst = intel_dp_sink_can_mst(intel_dp); > + bool sink_can_mst = drm_dp_has_mst(&intel_dp->aux, intel_dp->dpcd); > > drm_dbg_kms(&i915->drm, > "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n", > diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h > index 8b9eb4db3381c..2d8983a713e8c 100644 > --- a/include/drm/drm_dp_mst_helper.h > +++ b/include/drm/drm_dp_mst_helper.h > @@ -911,4 +911,26 @@ __drm_dp_mst_state_iter_get(struct drm_atomic_state *state, > for ((__i) = 0; (__i) < (__state)->num_private_objs; (__i)++) \ > for_each_if(__drm_dp_mst_state_iter_get((__state), &(mgr), NULL, &(new_state), (__i))) > > +/** > + * drm_dp_has_mst() - check whether or not a sink supports MST > + * @aux: The DP AUX channel to use > + * @dpcd: A cached copy of the DPCD capabilities for this sink > + * > + * Returns: %True if the sink supports MST, %false otherwise > + */ > +static inline bool > +drm_dp_has_mst(struct drm_dp_aux *aux, > + const u8 dpcd[DP_RECEIVER_CAP_SIZE]) > +{ > + u8 mstm_cap; > + > + if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_12) > + return false; > + > + if (drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &mstm_cap) != 1) > + return false; > + > + return !!(mstm_cap & DP_MST_CAP); > +} > + > #endif > -- > 2.26.2 > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Sean Paul, Software Engineer, Google / Chromium OS