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Message-ID: <20060520110739.93343.qmail@web25811.mail.ukl.yahoo.com>
Date: Sat, 20 May 2006 11:07:39 +0000 (GMT)
From: moreau francis <francis_moreau2000@yahoo.fr>
Reply-To: moreau francis <francis_moreau2000@yahoo.fr>
Subject: Re : [I2C] question on adapter design
To: Matti Aarnio <matti.aarnio@zmailer.org>
Cc: linux-kernel@vger.kernel.org
In-Reply-To: <20060519102347.GM8304@mea-ext.zmailer.org>
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>The I?C (TM Philips) -bus runs at 100 kHz or (high-speed one) at 400 kHz.
>An eight bit byte goes thru it in 80 or 20 microseconds depending on used
>speed.  If your interrupt processing considers it as medium level
>priority and fills the Tx fifo with as much as is available (most I?C TX
>sequences do fit inside the 8 byte fifo) and collects as much data as is
>available in the Rx fifo, you should be well set.

ok so most of I2C commands shouldn't last more than 160 us when bus 
runs at 400 khz, right ? If so, I'm not sure it worth to use interrupts because
an active polling would avoid context switch that is not negligible in that case.
Interrupts can be usefull if I2C transfers would be longer than 8 bytes...

>
>Most notable detail there is, that you do have those (for I?C) huge FIFOs.
>Another thing is (I haven't verified this) that I?C master controls the
>bus clock, and can stop it temporarily, when Tx FIFO is empty, or Rx FIFO
>is full.
>

Indeed, my controller can automatically stop the bus clock when Tx fifo is
empty or Rx fifo is full.


Francis


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