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[76.210.143.223]) by smtp.gmail.com with ESMTPSA id u15sm3011247pju.42.2020.08.20.13.44.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Aug 2020 13:44:57 -0700 (PDT) Date: Thu, 20 Aug 2020 13:44:57 -0700 (PDT) X-Google-Original-Date: Thu, 20 Aug 2020 13:35:38 PDT (-0700) Subject: Re: [PATCH 2/3] riscv: Define AT_VECTOR_SIZE_ARCH for ARCH_DLINFO In-Reply-To: <25223adbad5badb3cd0000df078b407bafc129fd.1593766028.git.zong.li@sifive.com> CC: Paul Walmsley , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, zong.li@sifive.com From: Palmer Dabbelt To: zong.li@sifive.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 03 Jul 2020 01:57:54 PDT (-0700), zong.li@sifive.com wrote: > AT_VECTOR_SIZE_ARCH should be defined with the maximum number of > NEW_AUX_ENT entries that ARCH_DLINFO can contain, but it wasn't defined > for RISC-V at all even though ARCH_DLINFO will contain one NEW_AUX_ENT > for the VDSO address. > > Signed-off-by: Zong Li > --- > arch/riscv/include/uapi/asm/auxvec.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/riscv/include/uapi/asm/auxvec.h b/arch/riscv/include/uapi/asm/auxvec.h > index d86cb17bbabe..22e0ae888406 100644 > --- a/arch/riscv/include/uapi/asm/auxvec.h > +++ b/arch/riscv/include/uapi/asm/auxvec.h > @@ -10,4 +10,7 @@ > /* vDSO location */ > #define AT_SYSINFO_EHDR 33 > > +/* entries in ARCH_DLINFO */ > +#define AT_VECTOR_SIZE_ARCH 1 > + > #endif /* _UAPI_ASM_RISCV_AUXVEC_H */ Reviewed-by: Palmer Dabbelt