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Date:   Sat, 22 Aug 2020 15:17:49 +0200
From:   Paul Cercueil <paul@crapouillou.net>
Subject: Re: [PATCH 00/13] MIPS: Convert Ingenic to a generic board
To:     "Maciej W. Rozycki" <macro@linux-mips.org>
Cc:     Zhou Yanjie <zhouyanjie@wanyeetech.com>,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
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Le sam. 22 ao=FBt 2020 =E0 3:29, Maciej W. Rozycki <macro@linux-mips.org>=20
a =E9crit :
> Hi Paul,
>=20
>>  > FAOD <cpu-feature-overrides.h> is not a hack, but an optimisation=20
>> measure
>>  > so that features known to be hardwired for a given machine/CPU do=20
>> not have
>>  > to be dynamically queried every time referred.  In some cases=20
>> that results
>>  > in large portions of code being optimised away by the compiler as=20
>> well.
>>=20
>>  Fair enough. Bloat-o-meter reports about ~100 KiB saved when that=20
>> file is
>>  present. But we can't use it in a generic kernel, unfortunately.
>=20
>  Well, run-time patching might be an alternative to get the best of=20
> both
> worlds, but someone would have to reimplement our feature selection=20
> system
> to use it.

Would run-time patching allow to drop dead code?

>>  > The hardcoded value for a feature defined in=20
>> <cpu-feature-overrides.h>
>>  > always has to be the same as one in the corresponding bit of the=20
>> `options'
>>  > member of `struct cpuinfo_mips', in this case MIPS_CPU_TLBINV.
>>=20
>>  In theory yes, in practice the CPU detection code is lagging=20
>> behind...
>=20
>  I wasn't aware of that.  In that case it has been a design abuse=20
> which
> has been missed by the maintainer when accepting patches.  It used to=20
> be
> the case that run-time detection was accurate and overrides were=20
> rather
> lazily added.
>=20
>  Also I note Ingenic must have had a CPU erratum if our=20
> `decode_configs'
> doesn't just work, as the interpretation of CP0.Config[5:0] registers=20
> has
> been architectural and mandatory, and that for a reason.  It's only=20
> legacy
> MIPS I-IV processors that should require special attention here.

Yes, Ingenic CPUs have a few bloopers here and there...

-Paul