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[178.255.168.35]) by smtp.gmail.com with ESMTPSA id a26sm7418266eje.78.2020.08.24.01.28.45 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 24 Aug 2020 01:28:46 -0700 (PDT) From: Michal Simek To: linux-kernel@vger.kernel.org, monstr@monstr.eu, michal.simek@xilinx.com, git@xilinx.com Cc: Krzysztof Kozlowski , Laurent Pinchart , Manish Narani , Michael Tretter , Nava kishore Manne , Rajan Vaja , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH] arm64: dts: zynqmp: Remove undocumented u-boot properties Date: Mon, 24 Aug 2020 10:28:45 +0200 Message-Id: <8ba339425b9c9f319bdedce7741367055a30713c.1598257720.git.michal.simek@xilinx.com> X-Mailer: git-send-email 2.28.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org u-boot, DT properties are not documented anywhere in Linux DT binding that's why remove them. Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 5 ----- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 1 - 2 files changed, 6 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index 9868ca15dfc5..c94c3bb67edc 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -10,35 +10,30 @@ #include / { pss_ref_clk: pss_ref_clk { - u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; video_clk: video_clk { - u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; pss_alt_ref_clk: pss_alt_ref_clk { - u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; gt_crx_ref_clk: gt_crx_ref_clk { - u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <108000000>; }; aux_ref_clk: aux_ref_clk { - u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index d1e9a5eb4f70..6a8ff4bcc09b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -131,7 +131,6 @@ zynqmp_power: zynqmp-power { }; zynqmp_clk: clock-controller { - u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,zynqmp-clk"; clocks = <&pss_ref_clk>, -- 2.28.0