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From:   Avri Altman <Avri.Altman@wdc.com>
To:     Adrian Hunter <adrian.hunter@intel.com>,
        "Martin K . Petersen" <martin.petersen@oracle.com>,
        "James E . J . Bottomley" <jejb@linux.ibm.com>
CC:     "linux-scsi@vger.kernel.org" <linux-scsi@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Alim Akhtar <alim.akhtar@samsung.com>
Subject: RE: [PATCH] scsi: ufs-pci: Add LTR support for Intel controllers
Thread-Topic: [PATCH] scsi: ufs-pci: Add LTR support for Intel controllers
Thread-Index: AQHWerh8jAraRVcWhEiaxLeTYGSkdKlJ5ztg
Date:   Wed, 26 Aug 2020 06:13:59 +0000
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References: <20200825081854.7222-1-adrian.hunter@intel.com>
In-Reply-To: <20200825081854.7222-1-adrian.hunter@intel.com>
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=20
>=20
> Intel host controllers support the setting of latency tolerance.
> Accordingly, implement the PM QoS ->set_latency_tolerance() callback. The
> raw register values are also exposed via debugfs.
>=20
> Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Avri Altman <avri.altman@wdc.com>

Some nits below.

Thanks,
Avri

> ---
>  drivers/scsi/ufs/ufshcd-pci.c | 122 +++++++++++++++++++++++++++++++++-
>  1 file changed, 120 insertions(+), 2 deletions(-)
>=20
> diff --git a/drivers/scsi/ufs/ufshcd-pci.c b/drivers/scsi/ufs/ufshcd-pci.=
c
> index 5a95a7bfbab0..e10f05013ae6 100644
> --- a/drivers/scsi/ufs/ufshcd-pci.c
> +++ b/drivers/scsi/ufs/ufshcd-pci.c
> @@ -13,6 +13,14 @@
>  #include "ufshcd.h"
>  #include <linux/pci.h>
>  #include <linux/pm_runtime.h>
> +#include <linux/pm_qos.h>
> +#include <linux/debugfs.h>
> +
> +struct intel_host {
> +       u32             active_ltr;
> +       u32             idle_ltr;
> +       struct dentry   *debugfs_root;
> +};
>=20
>  static int ufs_intel_disable_lcc(struct ufs_hba *hba)
>  {
> @@ -44,20 +52,129 @@ static int ufs_intel_link_startup_notify(struct ufs_=
hba
> *hba,
>         return err;
>  }
>=20
> +#define INTEL_ACTIVELTR                0x804
> +#define INTEL_IDLELTR          0x808
> +
> +#define INTEL_LTR_REQ          BIT(15)
> +#define INTEL_LTR_SCALE_MASK   GENMASK(11, 10)
> +#define INTEL_LTR_SCALE_1US    (2 << 10)
> +#define INTEL_LTR_SCALE_32US   (3 << 10)
> +#define INTEL_LTR_VALUE_MASK   GENMASK(9, 0)
> +
> +static void intel_cache_ltr(struct ufs_hba *hba)
> +{
> +       struct intel_host *host =3D ufshcd_get_variant(hba);
> +
> +       host->active_ltr =3D readl(hba->mmio_base + INTEL_ACTIVELTR);
> +       host->idle_ltr =3D readl(hba->mmio_base + INTEL_IDLELTR);
You might want to use the standard ufshcd_readl

> +}
> +
> +static void intel_ltr_set(struct device *dev, s32 val)
> +{
> +       struct ufs_hba *hba =3D dev_get_drvdata(dev);
> +       struct intel_host *host =3D ufshcd_get_variant(hba);
> +       u32 ltr;
> +
> +       pm_runtime_get_sync(dev);
> +
> +       /*
> +        * Program latency tolerance (LTR) accordingly what has been aske=
d
> +        * by the PM QoS layer or disable it in case we were passed
> +        * negative value or PM_QOS_LATENCY_ANY.
> +        */
> +       ltr =3D readl(hba->mmio_base + INTEL_ACTIVELTR);
> +
> +       if (val =3D=3D PM_QOS_LATENCY_ANY || val < 0) {
> +               ltr &=3D ~INTEL_LTR_REQ;
> +       } else {
> +               ltr |=3D INTEL_LTR_REQ;
> +               ltr &=3D ~INTEL_LTR_SCALE_MASK;
> +               ltr &=3D ~INTEL_LTR_VALUE_MASK;
> +
> +               if (val > INTEL_LTR_VALUE_MASK) {
> +                       val >>=3D 5;
> +                       if (val > INTEL_LTR_VALUE_MASK)
> +                               val =3D INTEL_LTR_VALUE_MASK;
> +                       ltr |=3D INTEL_LTR_SCALE_32US | val;
> +               } else {
> +                       ltr |=3D INTEL_LTR_SCALE_1US | val;
> +               }
> +       }
> +
> +       if (ltr =3D=3D host->active_ltr)
> +               goto out;
> +
> +       writel(ltr, hba->mmio_base + INTEL_ACTIVELTR);
> +       writel(ltr, hba->mmio_base + INTEL_IDLELTR);
> +
> +       /* Cache the values into intel_host structure */
> +       intel_cache_ltr(hba);
> +out:
> +       pm_runtime_put(dev);
> +}
> +
> +static void ufs_intel_ltr_expose(struct ufs_hba *hba)
> +{
> +       struct intel_host *host =3D ufshcd_get_variant(hba);
> +       struct dentry *dir =3D host->debugfs_root;
> +       struct device *dev =3D hba->dev;
> +
> +       dev->power.set_latency_tolerance =3D intel_ltr_set;
> +       dev_pm_qos_expose_latency_tolerance(dev);
> +
> +       intel_cache_ltr(hba);
> +
> +       debugfs_create_x32("active_ltr", 0444, dir, &host->active_ltr);
> +       debugfs_create_x32("idle_ltr", 0444, dir, &host->idle_ltr);
You might as well allow those values to be traced, e.g. use dev_pm_qos_upda=
te_user_latency_tolerance

> +}
> +
> +static void ufs_intel_ltr_hide(struct ufs_hba *hba)
> +{
> +       struct device *dev =3D hba->dev;
> +
> +       dev_pm_qos_hide_latency_tolerance(dev);
> +       dev->power.set_latency_tolerance =3D NULL;
> +}
> +
> +static int ufs_intel_common_init(struct ufs_hba *hba)
> +{
> +       struct device *dev =3D hba->dev;
> +       struct intel_host *host;
> +
> +       host =3D devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
> +       if (!host)
> +               return -ENOMEM;
> +       ufshcd_set_variant(hba, host);
> +       host->debugfs_root =3D debugfs_create_dir(dev_name(dev), NULL);
Maybe pack the debugfs code together, i.e. move this just above debugfs_cre=
ate_x32 ....

> +       ufs_intel_ltr_expose(hba);
> +       return 0;
> +}
> +
> +static void ufs_intel_common_exit(struct ufs_hba *hba)
> +{
> +       struct intel_host *host =3D ufshcd_get_variant(hba);
> +
> +       debugfs_remove_recursive(host->debugfs_root);
> +       ufs_intel_ltr_hide(hba);
> +}
> +
>  static int ufs_intel_ehl_init(struct ufs_hba *hba)
>  {
>         hba->quirks |=3D UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8;
> -       return 0;
> +       return ufs_intel_common_init(hba);
>  }
>=20
>  static struct ufs_hba_variant_ops ufs_intel_cnl_hba_vops =3D {
>         .name                   =3D "intel-pci",
> +       .init                   =3D ufs_intel_common_init,
> +       .exit                   =3D ufs_intel_common_exit,
>         .link_startup_notify    =3D ufs_intel_link_startup_notify,
>  };
>=20
>  static struct ufs_hba_variant_ops ufs_intel_ehl_hba_vops =3D {
>         .name                   =3D "intel-pci",
>         .init                   =3D ufs_intel_ehl_init,
> +       .exit                   =3D ufs_intel_common_exit,
>         .link_startup_notify    =3D ufs_intel_link_startup_notify,
>  };
>=20
> @@ -162,6 +279,8 @@ ufshcd_pci_probe(struct pci_dev *pdev, const struct
> pci_device_id *id)
>                 return err;
>         }
>=20
> +       pci_set_drvdata(pdev, hba);
> +
>         hba->vops =3D (struct ufs_hba_variant_ops *)id->driver_data;
>=20
>         err =3D ufshcd_init(hba, mmio_base, pdev->irq);
> @@ -171,7 +290,6 @@ ufshcd_pci_probe(struct pci_dev *pdev, const struct
> pci_device_id *id)
>                 return err;
>         }
>=20
> -       pci_set_drvdata(pdev, hba);
>         pm_runtime_put_noidle(&pdev->dev);
>         pm_runtime_allow(&pdev->dev);
>=20
> --
> 2.17.1