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[23.128.96.18]) by mx.google.com with ESMTP id i7si79636ejg.744.2020.08.26.15.50.22; Wed, 26 Aug 2020 15:50:46 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=2arXLmwR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726858AbgHZWsx (ORCPT + 99 others); Wed, 26 Aug 2020 18:48:53 -0400 Received: from mail.kernel.org ([198.145.29.99]:45358 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726071AbgHZWsw (ORCPT ); Wed, 26 Aug 2020 18:48:52 -0400 Received: from mail-ot1-f42.google.com (mail-ot1-f42.google.com [209.85.210.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 8824E207CD; Wed, 26 Aug 2020 22:48:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1598482130; bh=t9n5BChicvUvo0OvFPgATCF49zFJ4cpxQnjvAc2Mpx4=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=2arXLmwRzUtdI2UVgWMynafzCRBuzdYRglrl8HjeVBoJzhnPx7XW2YZrDyPUgvY4Q OVSJTbUqOhU4nGG0I14qbRO8QaMA0Q4oMckDcWsMoOLRryJm7mIsqMhJLHLsL+Cnq3 IdyatNHAQDCKjN9Lwix0wudliX/fyiVuBaEloc5A= Received: by mail-ot1-f42.google.com with SMTP id e23so2112235otk.7; Wed, 26 Aug 2020 15:48:50 -0700 (PDT) X-Gm-Message-State: AOAM531U501c+XUvYN96XzuACn300yyU++KlrxPLzmFOHBgl1QwOqYv2 DqZ3bapNwuC4coSQs6I/yXUoG0Dn74BM9kTQfQ== X-Received: by 2002:a05:6830:1d94:: with SMTP id y20mr4471094oti.129.1598482129883; Wed, 26 Aug 2020 15:48:49 -0700 (PDT) MIME-Version: 1.0 References: <6bd99d4a7e50904b57bb3ad050725fbb418874b7.1597852360.git.cristian.ciocaltea@gmail.com> <20200825220913.GA1423455@bogus> <20200826214220.GA2444747@BV030612LT> In-Reply-To: <20200826214220.GA2444747@BV030612LT> From: Rob Herring Date: Wed, 26 Aug 2020 16:48:38 -0600 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v5 1/3] dt-bindings: interrupt-controller: Add Actions SIRQ controller binding To: Cristian Ciocaltea Cc: Thomas Gleixner , Jason Cooper , Marc Zyngier , =?UTF-8?Q?Andreas_F=C3=A4rber?= , Manivannan Sadhasivam , "linux-kernel@vger.kernel.org" , devicetree@vger.kernel.org, "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , linux-actions@lists.infradead.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Aug 26, 2020 at 3:42 PM Cristian Ciocaltea wrote: > > Hi Rob, > > Thanks for the review! > > On Tue, Aug 25, 2020 at 04:09:13PM -0600, Rob Herring wrote: > > On Wed, Aug 19, 2020 at 07:37:56PM +0300, Cristian Ciocaltea wrote: > > > Actions Semi Owl SoCs SIRQ interrupt controller is found in S500, S700 > > > and S900 SoCs and provides support for handling up to 3 external > > > interrupt lines. > > > > > > Signed-off-by: Cristian Ciocaltea > > > --- > > > Changes in v5: > > > - Updated controller description statements both in the commit message > > > and the binding doc > > > > > > .../actions,owl-sirq.yaml | 68 +++++++++++++++++++ > > > 1 file changed, 68 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml > > > > > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml b/Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml > > > new file mode 100644 > > > index 000000000000..cf9b7a514e4e > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml > > > @@ -0,0 +1,68 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/interrupt-controller/actions,owl-sirq.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: Actions Semi Owl SoCs SIRQ interrupt controller > > > + > > > +maintainers: > > > + - Manivannan Sadhasivam > > > + - Cristian Ciocaltea > > > + > > > +description: | > > > + This interrupt controller is found in the Actions Semi Owl SoCs (S500, S700 > > > + and S900) and provides support for handling up to 3 external interrupt lines. > > > + > > > +properties: > > > + compatible: > > > + oneOf: > > > + - items: > > > + - enum: > > > + - actions,s500-sirq > > > + - actions,s700-sirq > > > + - actions,s900-sirq > > > + - const: actions,owl-sirq > > > + - const: actions,owl-sirq > > > > This should be dropped. You should always have the SoC specific > > compatible. > > Sure, I will get rid of the 'owl-sirq' compatible. > > > > + > > > + reg: > > > + maxItems: 1 > > > + > > > + interrupt-controller: true > > > + > > > + '#interrupt-cells': > > > + const: 2 > > > + description: > > > + The first cell is the input IRQ number, between 0 and 2, while the second > > > + cell is the trigger type as defined in interrupt.txt in this directory. > > > + > > > + 'actions,ext-interrupts': > > > + description: | > > > + Contains the GIC SPI IRQ numbers mapped to the external interrupt > > > + lines. They shall be specified sequentially from output 0 to 2. > > > + $ref: /schemas/types.yaml#/definitions/uint32-array > > > + minItems: 3 > > > + maxItems: 3 > > > > Can't you use 'interrupts' here? > > This was actually my initial idea, but it might confuse the users since > this is not following the parent controller IRQ specs, i.e. the trigger > type is set internally by the SIRQ driver, it's not taken from DT. Then what's the 2nd cell for? > Please see the DTS sample bellow where both devices are on the same > level and have GIC as interrupt parent. The 'interrupts' property > in the sirq node looks incomplete now. That is why I decided to use > a custom name for it, although I'm not sure it's the most relevant one, > I am open to any other suggestion. > > i2c0: i2c@b0170000 { > [...] > interrupts = ; > [...] > }; > > sirq: interrupt-controller@b01b0200 { > [...] > interrupt-controller; > #interrupt-cells = <2>; > interrupts = <13>, /* SIRQ0 */ > <14>, /* SIRQ1 */ > <15>; /* SIRQ2 */ This isn't valid if the GIC is the parent as you have to have 3 cells for each interrupt. Ultimately the GIC trigger type has to be something. Is it fixed or passed thru? If the latter, just use 0 (IRQ_TYPE_NONE) if the GIC trigger mode is not fixed. Having some sort of translation of the trigger is pretty common. Rob