Received: by 2002:a05:6a10:6006:0:0:0:0 with SMTP id w6csp433572pxa; Thu, 27 Aug 2020 06:29:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxGqs3dqrWJAKMx9j4AAJlAK7d90Qui45nPw5NFpwAzj41wkcnwwjBpNEWyQ1uVN6TDKkoe X-Received: by 2002:a17:906:fb01:: with SMTP id lz1mr17257304ejb.447.1598534955191; Thu, 27 Aug 2020 06:29:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598534955; cv=none; d=google.com; s=arc-20160816; b=MjkeTQeGZ/eqjpomY4uiv+rthVhCgwlj4RV+jbSWmk+vkIfDfMi4C8Ve1BvNvWVDSe zYRHOsn7Ze4l0RJdodR/xeiodNZo1SafmUJNuhv9o32V/usqI1ktG9SGV42pwPsDoLkR PLt7thfVKYO2z5xV5ouuXQWECblQ15JWjwpYPwPrma8KWiR464gRx3p/9pB3xPS8WXYR vk+KQ59MFESzedoZDTSc7rEH/peEwFtO+IJpER7DFHnshenqtAQRDWXDckB2dgg6VtsW mE8M9Qf270KnxMAOK+Gq04Zb2lp9lef3RQuimLmxSD/hth2v2KuBjgMt+nF9jYseU8Ch 3kEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=CFtXWVoDQRlsmnLtGiVTzXmr2cjKIhz3EbvE5N2btLM=; b=FvfczIJQLTUALnBAzfpHDu7oqpW4aK7I2x6A/m+Aid4MGlicgN9E93+oNy6OQ3bmdo z7BSglB5frEQoX9OilHfbw6MffRWF91PMivjCyH0gJ4cYrTry8MZ0hBmVaFLcsTwO4I1 sNFD7nqbwhfYmA26cQUu+FaQXO7Jq8xh6Kp3NhZjs/lQAb7lMW/uZgYgWcZsQqNUHEt2 N6utDrPMPr9MHrF1Y0yOmemaZfVZU+SI8SXPLRcA3UM3GnHEEPLel3beWLX4Q7OJhZ+u jUNNoqY61Xhzh9SrH/pM4QsLiE3rgtwjBuqay7tJk8gebV4dJ5QB83h1765gr8JJ4Tn2 hJGA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id i19si1392960ejg.457.2020.08.27.06.28.51; Thu, 27 Aug 2020 06:29:15 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727864AbgH0N1V (ORCPT + 99 others); Thu, 27 Aug 2020 09:27:21 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:10338 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727781AbgH0NTT (ORCPT ); Thu, 27 Aug 2020 09:19:19 -0400 Received: from DGGEMS409-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id C3F82C315B0D3867DA47; Thu, 27 Aug 2020 21:00:57 +0800 (CST) Received: from huawei.com (10.175.127.227) by DGGEMS409-HUB.china.huawei.com (10.3.19.209) with Microsoft SMTP Server id 14.3.487.0; Thu, 27 Aug 2020 21:00:46 +0800 From: Jason Yan To: , , , , CC: Hulk Robot Subject: [PATCH] video: fbdev: remove set but not used 'ulCoreClock' Date: Thu, 27 Aug 2020 21:00:28 +0800 Message-ID: <20200827130028.428893-1-yanaijie@huawei.com> X-Mailer: git-send-email 2.25.4 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.175.127.227] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This addresses the following gcc warning with "make W=1": drivers/video/fbdev/kyro/STG4000InitDevice.c: In function ‘SetCoreClockPLL’: drivers/video/fbdev/kyro/STG4000InitDevice.c:247:6: warning: variable ‘ulCoreClock’ set but not used [-Wunused-but-set-variable] // yanaijie fixed 247 | u32 ulCoreClock; | ^~~~~~~~~~~ Reported-by: Hulk Robot Signed-off-by: Jason Yan --- drivers/video/fbdev/kyro/STG4000InitDevice.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/video/fbdev/kyro/STG4000InitDevice.c b/drivers/video/fbdev/kyro/STG4000InitDevice.c index 1d3f2080aa6f..edaeec2d9590 100644 --- a/drivers/video/fbdev/kyro/STG4000InitDevice.c +++ b/drivers/video/fbdev/kyro/STG4000InitDevice.c @@ -244,7 +244,6 @@ int SetCoreClockPLL(volatile STG4000REG __iomem *pSTGReg, struct pci_dev *pDev) { u32 F, R, P; u16 core_pll = 0, sub; - u32 ulCoreClock; u32 tmp; u32 ulChipSpeed; @@ -282,7 +281,7 @@ int SetCoreClockPLL(volatile STG4000REG __iomem *pSTGReg, struct pci_dev *pDev) if (ulChipSpeed == 0) return -EINVAL; - ulCoreClock = ProgramClock(REF_FREQ, CORE_PLL_FREQ, &F, &R, &P); + ProgramClock(REF_FREQ, CORE_PLL_FREQ, &F, &R, &P); core_pll |= ((P) | ((F - 2) << 2) | ((R - 2) << 11)); -- 2.25.4