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Bottomley" CC: "linux-scsi@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Alim Akhtar Subject: RE: [PATCH V2] scsi: ufs-pci: Add LTR support for Intel controllers Thread-Topic: [PATCH V2] scsi: ufs-pci: Add LTR support for Intel controllers Thread-Index: AQHWfEKlBabm3VmckUqm60akqaE3LKlL3NPQ Date: Thu, 27 Aug 2020 12:08:37 +0000 Message-ID: References: <20200827072030.24655-1-adrian.hunter@intel.com> In-Reply-To: <20200827072030.24655-1-adrian.hunter@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=wdc.com; x-originating-ip: [212.25.79.133] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: dd27b8ae-b090-4f51-49bd-08d84a81edd4 x-ms-traffictypediagnostic: BY5PR04MB6613: x-microsoft-antispam-prvs: wdcipoutbound: EOP-TRUE x-ms-oob-tlc-oobclassifiers: OLM:1388; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: m2XuyDbnUY1/jY6I0LtqJ+7yKG+v2So+EhjdKRdnZD4a5p1yfHBv/gk0xy5hREsC0VEGi7lkn8qxmRzVmS5eB62JeAm7/O4kQbYk9Ax7RvJIxPPm0sZy/iG8OqN8qUSAQuHYLtH/PBKstPg/RgTsNo0KrYK0PMmf1GBkPyok/5XwwFNng3vkoYkngNcHuLApd3cduJynu8kuqTLi9lceSJ2pGTTkF4XmzS7ugX9Tt6ghjkmGkG99bg1nUpDoeOwT5EAEujAFa/pi+FReS7gQqu9EOP1jYHv29J12jVwexR1vQiuBf8b7oc+SMBwjcIssqDwJWFqIgUfavfqmT41vKA== x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:BY5PR04MB6705.namprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(4636009)(396003)(346002)(39860400002)(136003)(366004)(376002)(7696005)(4326008)(54906003)(316002)(9686003)(8936002)(55016002)(2906002)(110136005)(66446008)(64756008)(478600001)(76116006)(52536014)(86362001)(71200400001)(66556008)(66476007)(558084003)(26005)(186003)(66946007)(33656002)(5660300002)(8676002)(6506007);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata: T2a5UnJvA+xLyR1pxQCaEEKu0ZNmEptBA2BGEQObNfy9YxbUVM+TpquVIx1u5zuccSgl7wX8G06f1CnfWFC1h1Gs9BbFJ85tXxDAMWzT3MCwJ6WRmaakADJhKXszP/h1Ba3ri5BC8y+ZDN7l+zrY82C5mFli/0mj3QwPIpYTKp2ZbpI5Km7FoeJ/kOAU2y4DP1AksTROvyohDbZH+cLcDIo/fn1bVx1iv4P0yPwNpYCw1/GNCHN/qL+utUrl5CVxlowwVfiM1/1NHtXi5zEaJKT7SCW63v+zmsHVvtIeborardt8rpYFzmlE/hTOx7ggPmxQHOefknzOFpPuYlfI9rcqktcQU+ntH5jMaXH6JR2mNu/1xVtcPM6Vtpw1AneFGn+roC9ZDK+am6CJyCDlvvHD/idtXEfnZvbvB4A+EDpRxpB/dtht6+NrrJ0f6hu8px53a4u1zPrpMw7m1bdsYA74eolX8c8TYOW3JYR4ng/7eUaWPVoPGNKNUQJAt8rqK8XamJDmpZyLbZTPY5dIAaQ25B2jNDvPIkKjsgWhUicp0ZhO0G/mD7Bw0TOcdTF7hp7jxOG6TYVas/4jw0zwSe/pDxOBNFKVH2gx5yBmoZGV1rHnPN0Vl9H1w/MfDtNRb8yJefehrXFOM6ir+87E4Q== x-ms-exchange-transport-forked: True Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BY5PR04MB6705.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: dd27b8ae-b090-4f51-49bd-08d84a81edd4 X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Aug 2020 12:08:37.3099 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: vZQcFfbKxxhHziGgQuBBj8ZM7D5qS4OjngklyBcHRs/24HySMAzTUrT7pigY94b3vWlD+flcXSW/zKYUrs7y6Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR04MB6613 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org =20 >=20 > Intel host controllers support the setting of latency tolerance. > Accordingly, implement the PM QoS ->set_latency_tolerance() callback. The > raw register values are also exposed via debugfs. >=20 > Signed-off-by: Adrian Hunter Reviewed-by: Avri Altman