Received: by 2002:a05:6a10:6006:0:0:0:0 with SMTP id w6csp510714pxa; Thu, 27 Aug 2020 08:15:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwkdGlDHwLTXeCtPj2Ak4PjPDE3wIoyAi+8i1F2qwRl++yUO5XMxu876zy1wTpLXVp91OdO X-Received: by 2002:a17:906:bfcb:: with SMTP id us11mr11979864ejb.502.1598541358688; Thu, 27 Aug 2020 08:15:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598541358; cv=none; d=google.com; s=arc-20160816; b=wTAQ+4kb9yu63ZXXgQPbMHXshER+GfC1Wd6cfQqrfDjZ8ykYQ+SuAHtnlsg6qdAWDE jjWfuYO8QV/V5NoFcr/3ylathN14BZlh9VFlDCgK5F/5VpEJ9CTJ8blQgKHPzCE08pfR mm1aFqjnKpN31Ku4L8xy/IqRrtaXR/uGrUnlyMFeUfaAcLZG8ImPyACCZBtPFTwXItIc GNDpwSc8CR/a+4heBPeLmwXWZN+AS6zm4lZS5QnOW4+4gZYRk1xIkBRsMy/E4x974K/J Hb3vjRl7/VeEuJgrikThTUplnTb9do5l0jyaaBp6v0snBaTAVcgiS6/ZcrDFjPZx5OBb 6qcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding :content-language:in-reply-to:mime-version:user-agent:date :message-id:from:references:cc:to:subject; bh=JQAJMCiuUhZeOeLYWHt4ZHRrrpEQM6lcImSQJX2KP/4=; b=gVnoMWGW9QUmdvXciGR/pPJs7C2P+nvXiqgy2v+Bp7l09mEOAm2T34NOfDeny/SbPq 2a/Cs6VhPRNVb3G53N8PNyjKfv4H8AU25GLNwzS59Pm9YGSJ68yniHqwy9JfiyNnGTNp r75DSBOPyKGICRV2Hqvph1TCcaRKcluBxzmHoffqBj5BXt0rlfBiVGCJR3BKUABNJChv W4Q0IIm2TbbMSBk3eOSnFtkAA3l6WDT38/NthZ/abhrH3YKM2Kr5Xu1vGc6YPrX3kmAr a+0OcvwCPR19/w0gGoKwl8jBDnKQgH/odAvozDop3tvNBUzrkTeD53IHFXZZj3juNyXw b1Bw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id x2si1586004ejy.245.2020.08.27.08.15.35; Thu, 27 Aug 2020 08:15:58 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728202AbgH0PPH (ORCPT + 99 others); Thu, 27 Aug 2020 11:15:07 -0400 Received: from foss.arm.com ([217.140.110.172]:57244 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728478AbgH0LjV (ORCPT ); Thu, 27 Aug 2020 07:39:21 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0E8EF113E; Thu, 27 Aug 2020 04:15:08 -0700 (PDT) Received: from [192.168.1.190] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F18283F68F; Thu, 27 Aug 2020 04:15:05 -0700 (PDT) Subject: Re: [PATCH 26/35] kasan, arm64: Enable TBI EL1 To: Catalin Marinas Cc: Andrey Konovalov , Dmitry Vyukov , kasan-dev@googlegroups.com, Andrey Ryabinin , Alexander Potapenko , Marco Elver , Evgenii Stepanov , Elena Petrova , Branislav Rankov , Kevin Brodsky , Will Deacon , Andrew Morton , linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org References: <518da1e5169a4e343caa3c37feed5ad551b77a34.1597425745.git.andreyknvl@google.com> <20200827104033.GF29264@gaia> <9c53dfaa-119e-b12e-1a91-1f67f4aef503@arm.com> <20200827111344.GK29264@gaia> From: Vincenzo Frascino Message-ID: Date: Thu, 27 Aug 2020 12:17:19 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20200827111344.GK29264@gaia> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 8/27/20 12:13 PM, Catalin Marinas wrote: > On Thu, Aug 27, 2020 at 12:05:55PM +0100, Vincenzo Frascino wrote: >> On 8/27/20 11:40 AM, Catalin Marinas wrote: >>> On Fri, Aug 14, 2020 at 07:27:08PM +0200, Andrey Konovalov wrote: >>>> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S >>>> index 152d74f2cc9c..6880ddaa5144 100644 >>>> --- a/arch/arm64/mm/proc.S >>>> +++ b/arch/arm64/mm/proc.S >>>> @@ -38,7 +38,7 @@ >>>> /* PTWs cacheable, inner/outer WBWA */ >>>> #define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA >>>> >>>> -#ifdef CONFIG_KASAN_SW_TAGS >>>> +#if defined(CONFIG_KASAN_SW_TAGS) || defined(CONFIG_KASAN_HW_TAGS) >>>> #define TCR_KASAN_FLAGS TCR_TBI1 >>>> #else >>>> #define TCR_KASAN_FLAGS 0 >>> >>> I prefer to turn TBI1 on only if MTE is present. So on top of the v8 >>> user series, just do this in __cpu_setup. >> >> Not sure I understand... Enabling TBI1 only if MTE is present would break >> KASAN_SW_TAGS which is based on TBI1 but not on MTE. > > You keep the KASAN_SW_TAGS as above but for HW_TAGS, only set TBI1 later > in __cpu_setup(). > Ok, sounds good. -- Regards, Vincenzo