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[23.128.96.18]) by mx.google.com with ESMTP id i2si865459ejp.500.2020.08.28.07.54.22; Fri, 28 Aug 2020 07:54:46 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=m3SH83Jh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728010AbgH1Ovp (ORCPT + 99 others); Fri, 28 Aug 2020 10:51:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727979AbgH1Ovi (ORCPT ); Fri, 28 Aug 2020 10:51:38 -0400 Received: from mail-lj1-x242.google.com (mail-lj1-x242.google.com [IPv6:2a00:1450:4864:20::242]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58C70C061235 for ; Fri, 28 Aug 2020 07:51:35 -0700 (PDT) Received: by mail-lj1-x242.google.com with SMTP id m22so1623620ljj.5 for ; Fri, 28 Aug 2020 07:51:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ImiWhFwiMiRaDILGK2vYxwtK6H1QbPrDWNEB8Fo5yp0=; b=m3SH83JhPp5zysOZ8UGaOASaGvHwyBdy+dMZYhDz9IjeZrOUNDL7DGC2IYkYpae6UT FpGAiEisi2hdICi2QBwVlxCRBlQYajQ6kIl3apwv6Zd5zwaMsm+woTJe0VxhXsJCBmVB /Krz+up/rlea+pltJEx57NrY0mSwXBmgaoM8eBGVocnnO/EabniaNW7LYGT8om9EynVv CIC9WHLTJ4TqH3GGF/DLZDlPvjr7OZ+u5Gmua0OvS7bbxfJ/KVP9l6u2f80iB9oWA4S5 XcREjqO8mQbwzNglMH6NjTAUpG2SBhzd1ox2KvfQMgaZMf3Rcty3gxm60W7RrjIkgx2T DCMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ImiWhFwiMiRaDILGK2vYxwtK6H1QbPrDWNEB8Fo5yp0=; b=OEWooE3MV7ESZGpPC9qOwbGv0Mmd9aGdwYKdVlu3yAHHM1EmlyLPT3aAoNpZbz9Kds njflGjEASXw61DFFyLqD0LyvxFMwAmsmuHcCKIdT+q950/FdweT+TOr6Uy3WE9HBW1/Y sBcRIArJ6s98+OUFvCQzcsodbeyWrgSS2onHvEL15IC3ihACSPvaHZ6NhKL0f8obpxhj I48A58F2yi+FCOu7Ofs9qnv6KjSehNNIZudyYq0iLIO9VpuqJ6QcfpOClCRCzlwczeqs rLUzD3FEkM2uIDYLM1iNATVP2kFTTPw/bmUQBD0Ps76hSno6Zd7z1deGV48qdjm/cxuc sYzA== X-Gm-Message-State: AOAM531Hx9GP9hIEy6OrYJo1HF7rH/460ywCMINgydkeoTunhIkADKUU EbuGBNIYECs+6+ovZHtLjKlxixo3rb160SqOYc8vlg== X-Received: by 2002:a2e:9dd0:: with SMTP id x16mr1026817ljj.144.1598626291535; Fri, 28 Aug 2020 07:51:31 -0700 (PDT) MIME-Version: 1.0 References: <20200825193536.7332-1-krzk@kernel.org> <20200828130837.GA14163@kozik-lap> In-Reply-To: <20200828130837.GA14163@kozik-lap> From: Linus Walleij Date: Fri, 28 Aug 2020 16:51:20 +0200 Message-ID: Subject: Re: [PATCH v3 00/19] dt-bindings / arm64: Cleanup of i.MX 8 bindings To: Krzysztof Kozlowski Cc: Shawn Guo , Sascha Hauer , Fabio Estevam , Rob Herring , Bartosz Golaszewski , Pengutronix Kernel Team , NXP Linux Team , Ulf Hansson , Miquel Raynal , Mark Rutland , Thierry Reding , Anson Huang , Li Yang , Han Xu , Frank Li , Fugang Duan , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "linux-kernel@vger.kernel.org" , "open list:GPIO SUBSYSTEM" , Linux ARM , linux-mmc , linux-mtd@lists.infradead.org, linux-pwm@vger.kernel.org, "open list:SERIAL DRIVERS" , Linux PM list , LINUXWATCHDOG Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Aug 28, 2020 at 3:08 PM Krzysztof Kozlowski wrote: > On Fri, Aug 28, 2020 at 02:51:20PM +0200, Linus Walleij wrote: > > On Tue, Aug 25, 2020 at 9:35 PM Krzysztof Kozlowski wrote: > > > > > This is a v3 of cleanup of i.XM 8 bindings and DTSes. > > > > If you are going to be working a lot on Freescale SoC code going forward > > I wouldn't mind if you could add yourself as maintainer for the > > Freescale pin controller and GPIO at least, I already have high trust > > in you in general so if the Freescale maintainers also have that I think you > > should just sign up as maintainer. This makes it easier to do pull requests > > and things like that. > > Thanks for encouragement. Indeed I am planning to do more work around > i.MX 8M platforms from NXP/Freescale. However there are already four > maintainers for Freescale pin controller drivers so I doubt there is > need for fifth entry :). I beg to differ. As subsystem maintainer it has happened to me more than once that the i.MX pin control patches went unreviewed for weeks. Everyone listed for this driver is a kitchen sink maintainer that get way too much traffic and things fall over the edge. > Different question is the GPIO driver which apparently lacks entry in > Maintainers file. That's probably just an oversight. Feel free to add it! Yours, Linus Walleij