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From:   Sagar Kadam <sagar.kadam@openfive.com>
To:     "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
CC:     "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "robh+dt@kernel.org" <robh+dt@kernel.org>,
        "Paul Walmsley ( Sifive)" <paul.walmsley@sifive.com>,
        "palmer@dabbelt.com" <palmer@dabbelt.com>,
        "aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>,
        Yash Shah <yash.shah@openfive.com>
Subject: RE: [PATCH v2] dt-bindings: riscv: sifive-l2-cache: convert bindings
 to json-schema
Thread-Topic: [PATCH v2] dt-bindings: riscv: sifive-l2-cache: convert bindings
 to json-schema
Thread-Index: AQHWfVR4lz9JlE/ec0CZDYHYyLyKialNu0ZQ
Date:   Fri, 28 Aug 2020 16:49:23 +0000
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 <1598630453-31125-2-git-send-email-sagar.kadam@sifive.com>
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Hi,

Please ignore this v2, since the subject line missed the patch sequences 0/=
1 and 1/1.
Will resubmit it.

Thanks & BR,
Sagar

> -----Original Message-----
> From: Sagar Kadam <sagar.kadam@openfive.com>
> Sent: Friday, August 28, 2020 9:31 PM
> To: linux-kernel@vger.kernel.org
> Cc: linux-riscv@lists.infradead.org; devicetree@vger.kernel.org;
> robh+dt@kernel.org; Paul Walmsley ( Sifive) <paul.walmsley@sifive.com>;
> palmer@dabbelt.com; aou@eecs.berkeley.edu; Yash Shah
> <yash.shah@openfive.com>; Sagar Kadam <sagar.kadam@openfive.com>
> Subject: [PATCH v2] dt-bindings: riscv: sifive-l2-cache: convert bindings=
 to
> json-schema
>=20
> Convert the device tree bindings for the SiFive's FU540-C000 SoC's L2 Cac=
he
> controller to YAML format.
>=20
> Signed-off-by: Sagar Kadam <sagar.kadam@sifive.com>
> ---
>  .../devicetree/bindings/riscv/sifive-l2-cache.txt  | 51 ------------
> .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 92
> ++++++++++++++++++++++
>  2 files changed, 92 insertions(+), 51 deletions(-)  delete mode 100644
> Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt
>  create mode 100644 Documentation/devicetree/bindings/riscv/sifive-l2-
> cache.yaml
>=20
> diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt
> b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt
> deleted file mode 100644
> index 73d8f19..0000000
> --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt
> +++ /dev/null
> @@ -1,51 +0,0 @@
> -SiFive L2 Cache Controller
> ---------------------------
> -The SiFive Level 2 Cache Controller is used to provide access to fast co=
pies -
> of memory for masters in a Core Complex. The Level 2 Cache Controller als=
o
> -acts as directory-based coherency manager.
> -All the properties in ePAPR/DeviceTree specification applies for this
> platform
> -
> -Required Properties:
> ---------------------
> -- compatible: Should be "sifive,fu540-c000-ccache" and "cache"
> -
> -- cache-block-size: Specifies the block size in bytes of the cache.
> -  Should be 64
> -
> -- cache-level: Should be set to 2 for a level 2 cache
> -
> -- cache-sets: Specifies the number of associativity sets of the cache.
> -  Should be 1024
> -
> -- cache-size: Specifies the size in bytes of the cache. Should be 209715=
2
> -
> -- cache-unified: Specifies the cache is a unified cache
> -
> -- interrupts: Must contain 3 entries (DirError, DataError and DataFail
> signals)
> -
> -- reg: Physical base address and size of L2 cache controller registers m=
ap
> -
> -Optional Properties:
> ---------------------
> -- next-level-cache: phandle to the next level cache if present.
> -
> -- memory-region: reference to the reserved-memory for the L2 Loosely
> Integrated
> -  Memory region. The reserved memory node should be defined as per the
> bindings
> -  in reserved-memory.txt
> -
> -
> -Example:
> -
> -	cache-controller@2010000 {
> -		compatible =3D "sifive,fu540-c000-ccache", "cache";
> -		cache-block-size =3D <64>;
> -		cache-level =3D <2>;
> -		cache-sets =3D <1024>;
> -		cache-size =3D <2097152>;
> -		cache-unified;
> -		interrupt-parent =3D <&plic0>;
> -		interrupts =3D <1 2 3>;
> -		reg =3D <0x0 0x2010000 0x0 0x1000>;
> -		next-level-cache =3D <&L25 &L40 &L36>;
> -		memory-region =3D <&l2_lim>;
> -	};
> diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> new file mode 100644
> index 0000000..e14c8c6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> @@ -0,0 +1,92 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) # Copyright (C)
> +2020 SiFive, Inc.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SiFive L2 Cache Controller
> +
> +maintainers:
> +  - Sagar Kadam <sagar.kadam@sifive.com>
> +  - Yash Shah <yash.shah@sifive.com>
> +  - Paul Walmsley  <paul.walmsley@sifive.com>
> +
> +description:
> +  The SiFive Level 2 Cache Controller is used to provide access to fast
> +copies
> +  of memory for masters in a Core Complex. The Level 2 Cache Controller
> +also
> +  acts as directory-based coherency manager.
> +  All the properties in ePAPR/DeviceTree specification applies for this
> platform.
> +
> +allOf:
> +  - $ref: /schemas/cache-controller.yaml#
> +
> +properties:
> +  compatible:
> +    items:
> +     - enum:
> +        - sifive,fu540-c000-ccache
> +    description: |
> +      Should have "sifive,<soc>-cache" and "cache".
> +
> +  cache-block-size:
> +    const: 64
> +
> +  cache-level:
> +    const: 2
> +
> +  cache-sets:
> +    const: 1024
> +
> +  cache-size:
> +    const: 2097152
> +
> +  cache-unified: true
> +
> +  interrupts:
> +    description: |
> +      Must contain entries for DirError, DataError and DataFail signals.
> +    minItems: 1
> +    maxItems: 3
> +
> +  reg:
> +    maxItems: 1
> +    description: address of cache controller's registers.
> +
> +
> +  next-level-cache:
> +    description: |
> +      Phandle to the next level cache if present.
> +
> +  memory-region:
> +    description: |
> +      The reference to the reserved-memory for the L2 Loosely Integrated
> memory region.
> +      The reserved memory node should be defined as per the bindings in
> reserved-memory.txt.
> +
> +additionalProperties: false
> +
> +required:
> +  - compatible
> +  - cache-block-size
> +  - cache-level
> +  - cache-sets
> +  - cache-size
> +  - cache-unified
> +  - interrupts
> +  - reg
> +
> +examples:
> +  - |
> +    cache-controller@2010000 {
> +        compatible =3D "sifive,fu540-c000-ccache";
> +        cache-block-size =3D <64>;
> +        cache-level =3D <2>;
> +        cache-sets =3D <1024>;
> +        cache-size =3D <2097152>;
> +        cache-unified;
> +        reg =3D <0x2010000 0x1000>;
> +        interrupt-parent =3D <&plic0>;
> +        interrupts =3D <1 2 3>;
> +        next-level-cache =3D <&L25>;
> +        memory-region =3D <&l2_lim>;
> +    };
> --
> 2.7.4