Received: by 2002:a05:6a10:6006:0:0:0:0 with SMTP id w6csp1526623pxa; Fri, 28 Aug 2020 15:27:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxg25SsxCAb9/B21ZnUWMf0knlVmWIC9DXhcEsklYR85Md1qWLr+XJzaNJIHDoFnUQZJVm2 X-Received: by 2002:a50:fc83:: with SMTP id f3mr1006002edq.102.1598653652936; Fri, 28 Aug 2020 15:27:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598653652; cv=none; d=google.com; s=arc-20160816; b=cfGy9wusPi5jmRHfEcbWp3ytg2U5w9/ZVI8kexasoboKKObNDuzAhdF6qI9PeUeV+q +C9TDspHviRnZIBKM6BgNKD9/A5MvBwro8NQUwzgjr5+RgmVnAHz2I34/TQ1xHBiQpqh rW6TNYGe2RaAHbKhMCENsFh1It6jiIJXU2//3od2jHZoNm+qK0guexkjUbkT8GLanVN6 ARRYmN6xxwLkDfO/ebf8Kdp7bbs8xWZDKhxSVkBPETF86uJMkt7qcFQWlMeFyhzAFsSQ 9gVC/W0QF2xHYLJJJpmwXxq+OdUtsEgEFKZK4+Grhm0wh78u05pKCX0xtzJynzAfz2wL nDsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:dkim-signature:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from; bh=UXDpKI9QewAM3RzZ99bpRPC6DADHnDp3cxWP5RZlxM0=; b=Tr4OSfkqtUiT5XfgGiPCW248CeMu9mIkpfKDko9y1gRjPl2FEfOy6X+Eh+nYGtJdtO djUhQ1Ap5X4yqJ/WSz1qJDOyUG/qj8beYGf3GY8flJ6SeX8NueSBxzE2CHRl/5MPm2Cb 0+VHTCTbJ2RuZjgN06wOXbAPwudEpfI6zh+WNPaDZS4t5zF2NbusmRP7LkfZI8VTQUxn T0OHaSybjSna72oDScOkeQJ0np+ydSW5m9g0m7DA7Xnl7x7bCWg9z9ftcdih2Zzk0WSA vVufjJKwXcAHoIWUpu3ZYQZse5kBRI7IGf+zSoVUz7pZymZyaglgESy3f+DPtTKrk085 RchQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=gC73ZtBv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id i6si551590ejc.494.2020.08.28.15.27.10; Fri, 28 Aug 2020 15:27:32 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=gC73ZtBv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727810AbgH1W0T (ORCPT + 99 others); Fri, 28 Aug 2020 18:26:19 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:18106 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726594AbgH1WZ5 (ORCPT ); Fri, 28 Aug 2020 18:25:57 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 28 Aug 2020 15:25:10 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 28 Aug 2020 15:25:53 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 28 Aug 2020 15:25:53 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 28 Aug 2020 22:25:52 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 28 Aug 2020 22:25:52 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.174.186]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 28 Aug 2020 15:25:52 -0700 From: Sowjanya Komatineni To: , , , , CC: , , , , , Subject: [PATCH 4.19 6/7] arm64: tegra: Add missing timeout clock to Tegra194 SDMMC nodes Date: Fri, 28 Aug 2020 15:25:16 -0700 Message-ID: <1598653517-13658-7-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1598653517-13658-1-git-send-email-skomatineni@nvidia.com> References: <1598653517-13658-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1598653510; bh=UXDpKI9QewAM3RzZ99bpRPC6DADHnDp3cxWP5RZlxM0=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=gC73ZtBvz8G9FRt+wWDYgrTY3QUkcSrnV0I25XNAZYT3v0eZZTqpuW7u3wlV78c5Z G76Dd10iuXGI3nDw6i42NoMJU5A7d0EadvqPEOq8v7UtSjB8l3C/VlK0Jq/iPRDGcG O5KeMlJA+KYjuT/4jIeAUkW1KxRm+iMchQM+jR84fyApdQQkCbLewdhbIZNbTMTZbi 6SuUEEJz96G1cDUiKPn5bXjIA8zP8WpApW9P7OoeHtE06G58iuIg9OVnmE/WpthWiY b+MNHbLXO7XuvDK7TzdMZf8pwK3SxYLPa5FMdedX5TOnAjXnq+H/EIBiej/oqEDgL6 r2RWScY7T39pw== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org commit 5425fb15d8ee ("arm64: tegra: Add Tegra194 chip device tree") Tegra194 uses separate SDMMC_LEGACY_TM clock for data timeout and this clock is not enabled currently which is not recommended. Tegra194 SDMMC advertises 12Mhz as timeout clock frequency in host capability register. So, this clock should be kept enabled by SDMMC driver. Fixes: 5425fb15d8ee ("arm64: tegra: Add Tegra194 chip device tree") Cc: stable # 4.19 Tested-by: Jon Hunter Reviewed-by: Jon Hunter Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 9fc14bb..8a319c2 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -213,8 +213,9 @@ compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; reg = <0x03400000 0x10000>; interrupts = ; - clocks = <&bpmp TEGRA194_CLK_SDMMC1>; - clock-names = "sdhci"; + clocks = <&bpmp TEGRA194_CLK_SDMMC1>, + <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; + clock-names = "sdhci", "tmclk"; resets = <&bpmp TEGRA194_RESET_SDMMC1>; reset-names = "sdhci"; status = "disabled"; @@ -224,8 +225,9 @@ compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; reg = <0x03440000 0x10000>; interrupts = ; - clocks = <&bpmp TEGRA194_CLK_SDMMC3>; - clock-names = "sdhci"; + clocks = <&bpmp TEGRA194_CLK_SDMMC3>, + <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; + clock-names = "sdhci", "tmclk"; resets = <&bpmp TEGRA194_RESET_SDMMC3>; reset-names = "sdhci"; status = "disabled"; @@ -235,8 +237,9 @@ compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; reg = <0x03460000 0x10000>; interrupts = ; - clocks = <&bpmp TEGRA194_CLK_SDMMC4>; - clock-names = "sdhci"; + clocks = <&bpmp TEGRA194_CLK_SDMMC4>, + <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; + clock-names = "sdhci", "tmclk"; resets = <&bpmp TEGRA194_RESET_SDMMC4>; reset-names = "sdhci"; status = "disabled"; -- 2.7.4