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From:   Pekka Enberg <penberg@gmail.com>
Date:   Sun, 30 Aug 2020 11:01:22 +0300
Message-ID: <CAOJsxLHuX-nXFS6Dp+X=_hOrbT=-FUvWF_oM+6q508r=MNnFrQ@mail.gmail.com>
Subject: Re: [PATCH v3 3/3] riscv: Add cache information in AUX vector
To:     Zong Li <zong.li@sifive.com>
Cc:     Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        david.abdurachmanov@sifive.com,
        linux-riscv <linux-riscv@lists.infradead.org>,
        LKML <linux-kernel@vger.kernel.org>,
        Palmer Dabbelt <palmerdabbelt@google.com>
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On Fri, Aug 28, 2020 at 10:09 AM Zong Li <zong.li@sifive.com> wrote:
> +uintptr_t get_cache_geometry(u32 level, enum cache_type type)
> +{
> +       struct cacheinfo *this_leaf = get_cacheinfo(level, type);
> +       uintptr_t ret = (this_leaf->ways_of_associativity << 16 |
> +                        this_leaf->coherency_line_size);

You are dereferencing "this_leaf" without checking if it's NULL here.

> +
> +       return this_leaf ? ret : 0;
> +}

- Pekka