Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
Subject: Re: [PATCH 2/2] mtd: spi-nor: enable lock interface for macronix
 chips
To:     Ivan Mikhaylov <i.mikhaylov@yadro.com>
Cc:     Tudor Ambarus <tudor.ambarus@microchip.com>,
        Miquel Raynal <miquel.raynal@bootlin.com>,
        Richard Weinberger <richard@nod.at>,
        Vignesh Raghavendra <vigneshr@ti.com>,
        linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org
References: <20200812151818.16699-1-i.mikhaylov@yadro.com>
 <20200812151818.16699-3-i.mikhaylov@yadro.com>
From:   Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Message-ID: <ae094597-e57e-dff1-f897-bf3cc75f5511@prevas.dk>
Date:   Mon, 31 Aug 2020 12:55:16 +0200
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101
 Thunderbird/68.10.0
In-Reply-To: <20200812151818.16699-3-i.mikhaylov@yadro.com>
Content-Type: text/plain; charset=windows-1252
Content-Language: en-US
Content-Transfer-Encoding: 7bit
MIME-Version: 1.0
X-MS-Exchange-MessageSentRepresentingType: 1
Received: from [192.168.1.149] (5.186.112.31) by AM3PR07CA0110.eurprd07.prod.outlook.com (2603:10a6:207:7::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3348.5 via Frontend Transport; Mon, 31 Aug 2020 10:55:17 +0000
X-Originating-IP: [5.186.112.31]
X-MS-PublicTrafficType: Email
X-MS-Office365-Filtering-Correlation-Id: 8aec64e9-4109-47e8-30a5-08d84d9c58cf
X-MS-TrafficTypeDiagnostic: AM0PR10MB3220:
X-Microsoft-Antispam-PRVS: <AM0PR10MB3220DCBEE627A004DCCE22D193510@AM0PR10MB3220.EURPRD10.PROD.OUTLOOK.COM>
X-MS-Oob-TLC-OOBClassifiers: OLM:913;
X-MS-Exchange-SenderADCheck: 1
X-Microsoft-Antispam: BCL:0;
X-Microsoft-Antispam-Message-Info: pRk3KABxRVg3Hhn0oq1Z8Q6GoadwZPc34iBhzTRD6QbIO8qdPvjFmCqz+hfTqARRKCVyST0wWRJLDqJ/Q+SiPKo9Luh90AVEH6wiUIdk3AylJVxFXuFGbQw1PddGzvigl+83vihF8q2C7Obg9AvboqnsZXa4NiNUJEQOur3QD5wsRnZTGaT54EPuSuBN+NwfHC16FofwNjgx+0IXY0mJAtEcsJz6V47H1Usf1VAbjZw9lJtKuCqGKfrFi3bfPciy9xVHyyW5wzmRsa2JL2nYkszizF3BQ6bM1QGDhp4xMVsqRNrYIMlgm72ggyEe3mtBPl48Wl86XEIEluddrUev5vl2Qh4+NdKykk0aUVNnLB2d67T85WSmzC9BnJP5pQEMLbAkUY3P+NIZKDKpmPuWEUOgVjGY58wRdHnMIYBy17BRwVHKfbdhVeL8o8ANd/iP3QIh2sN40oyqKeDS4VqOAw==
X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:AM0PR10MB1874.EURPRD10.PROD.OUTLOOK.COM;PTR:;CAT:NONE;SFS:(396003)(346002)(136003)(376002)(366004)(39840400004)(36756003)(6486002)(86362001)(6916009)(2906002)(478600001)(16526019)(44832011)(316002)(31696002)(16576012)(26005)(8976002)(66556008)(66946007)(66476007)(31686004)(8676002)(8936002)(186003)(4744005)(956004)(2616005)(5660300002)(52116002)(83380400001)(54906003)(4326008)(43740500002);DIR:OUT;SFP:1102;
X-MS-Exchange-AntiSpam-MessageData: alZ8h0jsy2eUGzO1tL+ROp/9E4Stm4eZt4/8oj2xO2NzlK1MM28AKk0LuMJYEkBtiyez1mS5WNiYiS4Xo0H5MxzHa8RhbW8UbZ/wl/h/qHVkjYGthMmL5+sjNIlMIUZu7JdXbHu8uoMoTcioPcTU52EovtfJqqaUFMOwJvi2ZcsMRv7Dugezfo0Ib2ulmx+QbusMLfqSNlHOVUcfYLyb8Q8NjZtL+5Y5o/HM1/MEcK/oIE1vi13mRU3k/MdlPj+k8637mLseiSt8eaCnj+gpw3WIObFDWS5seufodLNlbxky9VfFTBcZeV4tTzO4cOGrv//jksE7o7vZLRlo4v58Qgnj/v3O34hWtO7JBcE6tgAgx9jj76LXQpe6PObpxGVH2NEQjlCPwA0h+TrdcRW7AUQ8Cp95VvNBWjm8Kz54l3y9YxvhrEasP3cwxJDeC5EnlIPn8HVX3tl0IKO5PdUyYPj4Zw97iqxIpB9OuWIWJrnPGkK0fueLCD/Nymn2DLJ5IaIHuouodtk7EXP2MFeXYT1arx2S5ezC+Fo9CNoyDFViIFhSPfY5XgiMLmG0WEqxltvHxf+DwiB3CEmz4uD2rmm+E9J36OCjCxlPGWfzRKKaPinKugq7sLioJKr2l9LlG8jhVnW/2yitenrKpfI89Q==
X-OriginatorOrg: prevas.dk
X-MS-Exchange-CrossTenant-Network-Message-Id: 8aec64e9-4109-47e8-30a5-08d84d9c58cf
X-MS-Exchange-CrossTenant-AuthSource: AM0PR10MB1874.EURPRD10.PROD.OUTLOOK.COM
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Aug 2020 10:55:17.5853
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: d350cf71-778d-4780-88f5-071a4cb1ed61
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: rGXiZP2GDPBPSbiivwiHFmGgbnAcgoBD04ehrPiP0MNePLh+H0nW/aBT6KYVE7GFD1/kpQEaRG6M28+J2WShbSBYbzrtnJ+4gkR8qHf5ChE=
X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR10MB3220
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On 12/08/2020 17.18, Ivan Mikhaylov wrote:
> Add locks for whole macronix chip series with BP0-2 and BP0-3 bits.
> 
> Tested with mx25l51245g(BP0-3).

Hmm. I've tried adding support for locking on Macronix to U-Boot
(https://patchwork.ozlabs.org/project/uboot/patch/20200326114257.1782-3-rasmus.villemoes@prevas.dk/),
but that was quite a bit more involved than this. Note in particular the
first part of my commit message:

  Macronix chips implements locking in (power-of-two multiple of) 64K
  blocks, not as a fraction of the chip's size.

At least, that was true for the chip I was interested in and the few
others whose data sheets I grabbed to double-check. So I'm a bit
skeptical that this can work out-of-the-box without introducing a new
struct spi_nor_locking_ops.

Rasmus