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[34.197.84.77]) by smtp.gmail.com with ESMTPSA id y73sm10600006qkb.23.2020.08.31.11.19.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 11:19:19 -0700 (PDT) Date: Mon, 31 Aug 2020 18:19:18 +0000 From: Bjorn Andersson To: Maulik Shah Cc: maz@kernel.org, linus.walleij@linaro.org, swboyd@chromium.org, evgreen@chromium.org, mka@chromium.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, agross@kernel.org, tglx@linutronix.de, jason@lakedaemon.net, dianders@chromium.org, rnayak@codeaurora.org, ilina@codeaurora.org, lsrao@codeaurora.org Subject: Re: [PATCH v5 2/6] pinctrl: qcom: Use return value from irq_set_wake() call Message-ID: <20200831181918.GB468@uller> References: <1598113021-4149-1-git-send-email-mkshah@codeaurora.org> <1598113021-4149-3-git-send-email-mkshah@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1598113021-4149-3-git-send-email-mkshah@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat 22 Aug 16:16 UTC 2020, Maulik Shah wrote: > msmgpio irqchip was not using return value of irq_set_irq_wake() callback > since previously GIC-v3 irqchip neither had IRQCHIP_SKIP_SET_WAKE flag nor > it implemented .irq_set_wake callback. This lead to irq_set_irq_wake() > return error -ENXIO. > > However from 'commit 4110b5cbb014 ("irqchip/gic-v3: Allow interrupt to be > configured as wake-up sources")' GIC irqchip has IRQCHIP_SKIP_SET_WAKE > flag. > > Use return value from irq_set_irq_wake() and irq_chip_set_wake_parent() > instead of always returning success. > > Fixes: e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy") > Signed-off-by: Maulik Shah > Reviewed-by: Douglas Anderson > Reviewed-by: Stephen Boyd Acked-by: Bjorn Andersson > --- > drivers/pinctrl/qcom/pinctrl-msm.c | 8 +++----- > 1 file changed, 3 insertions(+), 5 deletions(-) > > diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c > index 1c23f5c..1df2322 100644 > --- a/drivers/pinctrl/qcom/pinctrl-msm.c > +++ b/drivers/pinctrl/qcom/pinctrl-msm.c > @@ -1077,12 +1077,10 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) > * when TLMM is powered on. To allow that, enable the GPIO > * summary line to be wakeup capable at GIC. > */ > - if (d->parent_data) > - irq_chip_set_wake_parent(d, on); > - > - irq_set_irq_wake(pctrl->irq, on); > + if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) > + return irq_chip_set_wake_parent(d, on); > > - return 0; > + return irq_set_irq_wake(pctrl->irq, on); > } > > static int msm_gpio_irq_reqres(struct irq_data *d) > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation >