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Tue, 1 Sep 2020 13:15:06 +0900 (KST) Received: from epsmtrp1.samsung.com (unknown [182.195.40.13]) by epcas1p4.samsung.com (KnoxPortal) with ESMTPA id 20200901041505epcas1p4f6bb868de0beb554e708f9aa3a578f6d~wjbvChLbr1010310103epcas1p4_; Tue, 1 Sep 2020 04:15:05 +0000 (GMT) Received: from epsmgms1p2.samsung.com (unknown [182.195.42.42]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20200901041505epsmtrp17553141b8b96e2004732a83f30a11e8b~wjbvBQs890331203312epsmtrp1w; Tue, 1 Sep 2020 04:15:05 +0000 (GMT) X-AuditID: b6c32a35-5edff70000004a22-ac-5f4dcaca9505 Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p2.samsung.com (Symantec Messaging Gateway) with SMTP id 28.40.08303.9CACD4F5; Tue, 1 Sep 2020 13:15:05 +0900 (KST) Received: from [10.113.221.102] (unknown [10.113.221.102]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20200901041504epsmtip213960aef21407382983f4a7ead95547a~wjbupowAQ1597015970epsmtip2_; Tue, 1 Sep 2020 04:15:04 +0000 (GMT) Subject: Re: [PATCH v2 2/4] drm/vc4: hdmi: Add pixel bvb clock control To: Hoegeun Kwon , nsaenzjulienne@suse.de, eric@anholt.net, maxime@cerno.tech, stefan.wahren@i2se.com, dave.stevenson@raspberrypi.com Cc: devicetree@vger.kernel.org, tim.gover@raspberrypi.com, sboyd@kernel.org, mturquette@baylibre.com, kdasu.kdev@gmail.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org, robh+dt@kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-rpi-kernel@lists.infradead.org, phil@raspberrypi.com, linux-arm-kernel@lists.infradead.org From: Chanwoo Choi Organization: Samsung Electronics Message-ID: <46e051f7-ba72-5960-da95-a2e9c44d2d85@samsung.com> Date: Tue, 1 Sep 2020 13:27:33 +0900 User-Agent: Mozilla/5.0 (X11; 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charset="utf-8" X-Sendblock-Type: SVC_REQ_APPROVE CMS-TYPE: 101P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20200901040851epcas1p3124094e38175758b2310bdae6d76793c References: <20200901040759.29992-1-hoegeun.kwon@samsung.com> <20200901040759.29992-3-hoegeun.kwon@samsung.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Hoegeun, It looks good to me. But, just one comment. On 9/1/20 1:07 PM, Hoegeun Kwon wrote: > There is a problem that the output does not work at a resolution > exceeding FHD. To solve this, we need to adjust the bvb clock at a > resolution exceeding FHD. > > Signed-off-by: Hoegeun Kwon > --- > drivers/gpu/drm/vc4/vc4_hdmi.c | 25 +++++++++++++++++++++++++ > drivers/gpu/drm/vc4/vc4_hdmi.h | 1 + > 2 files changed, 26 insertions(+) > > diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c > index 95ec5eedea39..eb3192d1fd86 100644 > --- a/drivers/gpu/drm/vc4/vc4_hdmi.c > +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c > @@ -80,6 +80,7 @@ > # define VC4_HD_M_ENABLE BIT(0) > > #define CEC_CLOCK_FREQ 40000 > +#define VC4_HSM_MID_CLOCK 149985000 > > static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) > { > @@ -380,6 +381,7 @@ static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder) > HDMI_WRITE(HDMI_VID_CTL, > HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); > > + clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); > clk_disable_unprepare(vc4_hdmi->hsm_clock); > clk_disable_unprepare(vc4_hdmi->pixel_clock); > > @@ -638,6 +640,23 @@ static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder) > return; > } > > + ret = clk_set_rate(vc4_hdmi->pixel_bvb_clock, > + (hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000)); > + if (ret) { > + DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret); > + clk_disable_unprepare(vc4_hdmi->hsm_clock); > + clk_disable_unprepare(vc4_hdmi->pixel_clock); > + return; > + } > + > + ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); > + if (ret) { > + DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret); > + clk_disable_unprepare(vc4_hdmi->hsm_clock); > + clk_disable_unprepare(vc4_hdmi->pixel_clock); > + return; > + } Generally, enable the clock before using clk and then change the clock rate. I think that you better to change the order between clk_prepare_enable and clk_set_rate. > + > if (vc4_hdmi->variant->reset) > vc4_hdmi->variant->reset(vc4_hdmi); > > @@ -1593,6 +1612,12 @@ static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) > return PTR_ERR(vc4_hdmi->audio_clock); > } > > + vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb"); > + if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) { > + DRM_ERROR("Failed to get pixel bvb clock\n"); > + return PTR_ERR(vc4_hdmi->pixel_bvb_clock); > + } > + > vc4_hdmi->reset = devm_reset_control_get(dev, NULL); > if (IS_ERR(vc4_hdmi->reset)) { > DRM_ERROR("Failed to get HDMI reset line\n"); > diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h > index 0806c6d9f24e..63c6f8bddf1d 100644 > --- a/drivers/gpu/drm/vc4/vc4_hdmi.h > +++ b/drivers/gpu/drm/vc4/vc4_hdmi.h > @@ -147,6 +147,7 @@ struct vc4_hdmi { > struct clk *pixel_clock; > struct clk *hsm_clock; > struct clk *audio_clock; > + struct clk *pixel_bvb_clock; > > struct reset_control *reset; > > -- Best Regards, Chanwoo Choi Samsung Electronics