Received: by 2002:a05:6a10:22f:0:0:0:0 with SMTP id 15csp1861218pxk; Tue, 1 Sep 2020 09:27:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw1nL/90O32W3mrQ4lOEKIat11mLr+clWbKAXMDwmoujL+PmYZmzR7OBuRU5XBtHvovoiWj X-Received: by 2002:a17:906:cc8d:: with SMTP id oq13mr2163643ejb.280.1598977625178; Tue, 01 Sep 2020 09:27:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598977625; cv=none; d=google.com; s=arc-20160816; b=kofUV9qfM4VfCGcJXyxZr9gE5g77DjnDWrA9jTaqfrAbkZDjwXAvDbPxAs01ajdDVU UVwCi0iAWAQlyKKvFWKDs7rf2ltr4z00s4wEiEJp9wFabzBn+PvKf5aePz9rj/IypVHu +Fof5sX36MTxwLjV/yQNEQoeQOEClg8ONndyyIU8s6YgXihFzoh/VQnEqno+vBnHp80t tacsDtM3hAlcEDhK8di65CTSKNemfNnzRk95yVLQg+M5r9G0HmZ/RBLew/kTl/dqo8l+ pyW+dlvcbXB6BfvnCpDHnNuNs/3Bp3yWB32+LMy4Zrc4DyBW4Q9k+ze4KB99ueYW0ocF GlEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:dkim-signature:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from; bh=hYsZs3PFx3eixB8zWm5MxRB8KNm72Tw8kvyR/ZyLQDY=; b=ItFzJg8aHDNLXorTt5TdEJ4MfskAO1UhxnHaW9WbsmGdkRKwdx28gvlUPj5LeIyFQf Y7g3VzRyhSMAI2CB3/xFX+29Eo8MvfUfRJz2V+lg4hWF2iHuCtmqzBZFiZZoPo4KIdD5 UJX8IjSsXRG/suVLLVxSWo0yorcvFNjil1nxhKW16kk76ZZuvMDcl00Fq4li+o9JJgwn d8tldDPHiY5eb2XrQjBiiGqamonxy2yKW4dGCHRHPtK8lskw/J7i7IBXakzu5w3mPokH j/wG2u6HyOUu6Ph4Rk6EvMAAjPHx/wLWVm+Gy7ouTXOEGjUdxkfD0Ef4g2xbX9cqkK2F AF1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=rNpabDcm; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id q8si938586ejm.507.2020.09.01.09.26.41; Tue, 01 Sep 2020 09:27:05 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=rNpabDcm; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731977AbgIAQZc (ORCPT + 99 others); Tue, 1 Sep 2020 12:25:32 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:12019 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731104AbgIAQZY (ORCPT ); Tue, 1 Sep 2020 12:25:24 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 01 Sep 2020 09:24:34 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 01 Sep 2020 09:25:21 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 01 Sep 2020 09:25:21 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 1 Sep 2020 16:25:19 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 1 Sep 2020 16:25:19 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.173.243]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 01 Sep 2020 09:25:18 -0700 From: Sowjanya Komatineni To: , , , , CC: , , , , , Subject: [PATCH v2 4.19 5/7] arm64: tegra: Add missing timeout clock to Tegra186 SDMMC nodes Date: Tue, 1 Sep 2020 09:24:48 -0700 Message-ID: <1598977490-1826-6-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1598977490-1826-1-git-send-email-skomatineni@nvidia.com> References: <1598977490-1826-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1598977475; bh=hYsZs3PFx3eixB8zWm5MxRB8KNm72Tw8kvyR/ZyLQDY=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=rNpabDcminKZESuxA7an0et29CbKTK9CL1YAkO0Bf+TQD9Z2XnL+2hD8HUoeAql3W Kd1Uc9jRW53rqvahLoCSwEp38Pnu4bR2REz8+SWtfUyyBAPFRnk2QTDNo+73iugjnB mHhLzPMimZNBMnDdKulhAB1Q8xF0QJCJmu3r1I9drPlLPmOFNYTaXJGbpXwzsjtov1 LnRDgAz6wQD2xQUJV/TcVwhgxiBUmNZ/1+IrvbfB2+2e31Ov3VQIZpWP66FsycJLe5 LMtVdgZiVmOadKfsfK962YvWOitaOPQOHkPXYu/gZyoE3BO5sho6qZVmQuATDXmAsw L4R9SpqD+2cdg== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Tegra186 uses separate SDMMC_LEGACY_TM clock for data timeout and this clock was not enabled when Tegra186 support was added to the driver in commit 39cb62cb8973 ("arm64: tegra: Add Tegra186 support") which is not recommended. Tegra186 SDMMC advertises 12Mhz as timeout clock frequency in host capability register and uses it by default. So, this clock should be kept enabled by the SDMMC driver. Fixes: 39cb62cb8973 ("arm64: tegra: Add Tegra186 support") Cc: stable # 4.19 Tested-by: Jon Hunter Reviewed-by: Jon Hunter Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index b762227..821dc5f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -232,8 +232,9 @@ compatible = "nvidia,tegra186-sdhci"; reg = <0x0 0x03400000 0x0 0x10000>; interrupts = ; - clocks = <&bpmp TEGRA186_CLK_SDMMC1>; - clock-names = "sdhci"; + clocks = <&bpmp TEGRA186_CLK_SDMMC1>, + <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; + clock-names = "sdhci", "tmclk"; resets = <&bpmp TEGRA186_RESET_SDMMC1>; reset-names = "sdhci"; status = "disabled"; @@ -243,8 +244,9 @@ compatible = "nvidia,tegra186-sdhci"; reg = <0x0 0x03420000 0x0 0x10000>; interrupts = ; - clocks = <&bpmp TEGRA186_CLK_SDMMC2>; - clock-names = "sdhci"; + clocks = <&bpmp TEGRA186_CLK_SDMMC2>, + <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; + clock-names = "sdhci", "tmclk"; resets = <&bpmp TEGRA186_RESET_SDMMC2>; reset-names = "sdhci"; status = "disabled"; @@ -254,8 +256,9 @@ compatible = "nvidia,tegra186-sdhci"; reg = <0x0 0x03440000 0x0 0x10000>; interrupts = ; - clocks = <&bpmp TEGRA186_CLK_SDMMC3>; - clock-names = "sdhci"; + clocks = <&bpmp TEGRA186_CLK_SDMMC3>, + <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; + clock-names = "sdhci", "tmclk"; resets = <&bpmp TEGRA186_RESET_SDMMC3>; reset-names = "sdhci"; status = "disabled"; @@ -265,8 +268,9 @@ compatible = "nvidia,tegra186-sdhci"; reg = <0x0 0x03460000 0x0 0x10000>; interrupts = ; - clocks = <&bpmp TEGRA186_CLK_SDMMC4>; - clock-names = "sdhci"; + clocks = <&bpmp TEGRA186_CLK_SDMMC4>, + <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; + clock-names = "sdhci", "tmclk"; resets = <&bpmp TEGRA186_RESET_SDMMC4>; reset-names = "sdhci"; status = "disabled"; -- 2.7.4