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[23.128.96.18]) by mx.google.com with ESMTP id bt10si2746135edb.554.2020.09.02.08.59.19; Wed, 02 Sep 2020 08:59:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=rReJtTJH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727788AbgIBP6Y (ORCPT + 99 others); Wed, 2 Sep 2020 11:58:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726397AbgIBP6V (ORCPT ); Wed, 2 Sep 2020 11:58:21 -0400 Received: from mail-il1-x143.google.com (mail-il1-x143.google.com [IPv6:2607:f8b0:4864:20::143]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D769C061244 for ; Wed, 2 Sep 2020 08:58:21 -0700 (PDT) Received: by mail-il1-x143.google.com with SMTP id h11so5419259ilj.11 for ; Wed, 02 Sep 2020 08:58:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=+JoguK0t2hKxuhREswBqHNa7tuob+XzJi0Xu9ksbpOc=; b=rReJtTJH7H7q/P1Yom+QXMk15rqMDzxkVaPh9Td1/uWRnk1F/A6Mjslb9LwaU2jC9e svrwJysDQmoM/d3Ha1BLlLynPAZLKUQNR+3la866X/Q/fW6sKVulL4gO61GrbaolHJsG JDF1ZA0PL7HhngVmRq93O0S+ZWIubzUjI7Pl4arNEW65+Rv9+Bfls0dxqu4yxj/pzb1V IsKaaZDHDki/DLcRiFxHxIUhIB9FlpbZrpXfs9UwfqT/CunIbpE7hQZ+8TklydKPVxTX 1/KL2VWYw5TuY0qKW7iTNq80KjnyMGn/MrMnRKSv4SZk6+DfCl5idO6dn4SoM7MdHvDO d66g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=+JoguK0t2hKxuhREswBqHNa7tuob+XzJi0Xu9ksbpOc=; b=H9XtX/Oj4/P3ed6WLm+Q4gSwDl77qO8xZM8rSxC4ImyhwJY1WfMSVdzqX+YeQj08K+ gPkJsd8F0TUd47ydb98hO3V+Uvy57BRqLwErVvQbith5DstDdf6hKlKyzCdUdtl5jd1u r+F/pi2G6L8yD6k2jNZ5IkAgQ6PT4YevNhN6Pyi3T+n+Uz0pY6nENkULUnHmiIuSLsBK +xM5IP2HoPbX57+1nqdvotwutMTVqwP2DwAwPjfobG0m5mhcS1GHvdJNLunCuoBnfpEj WI4pXClcxq6xR15YOFNoNNQT5YrsTuU65ErOeSbJOHqk5/DH68zetSNtMK0rNqRnWvXn 228g== X-Gm-Message-State: AOAM531oYxW1mG1MglucysJ4YzdxLfbKIanUDmMzX5A18z7f6BUFhzDc 5hsAlFA8ouTdzHK46PlouWaKgBukbaIX5O37BQ== X-Received: by 2002:a92:6a09:: with SMTP id f9mr4251600ilc.273.1599062300407; Wed, 02 Sep 2020 08:58:20 -0700 (PDT) MIME-Version: 1.0 References: <20200902132549.496605622@infradead.org> <20200902133200.666781610@infradead.org> In-Reply-To: <20200902133200.666781610@infradead.org> From: Brian Gerst Date: Wed, 2 Sep 2020 11:58:09 -0400 Message-ID: Subject: Re: [PATCH 01/13] x86/entry: Fix AC assertion To: Peter Zijlstra Cc: "the arch/x86 maintainers" , Linux Kernel Mailing List , Kyle Huey , Alexandre Chartre , "Robert O'Callahan" , "Paul E. McKenney" , Frederic Weisbecker , Paolo Bonzini , Sean Christopherson , Masami Hiramatsu , Petr Mladek , Steven Rostedt , Joel Fernandes , Boris Ostrovsky , Juergen Gross , Andy Lutomirski , Josh Poimboeuf , Daniel Thompson , Andrew Cooper Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Sep 2, 2020 at 9:38 AM Peter Zijlstra wrote: > > From: Peter Zijlstra > > The WARN added in commit 3c73b81a9164 ("x86/entry, selftests: Further > improve user entry sanity checks") unconditionally triggers on my IVB > machine because it does not support SMAP. > > For !SMAP hardware we patch out CLAC/STAC instructions and thus if > userspace sets AC, we'll still have it set after entry. > > Fixes: 3c73b81a9164 ("x86/entry, selftests: Further improve user entry sanity checks") > Signed-off-by: Peter Zijlstra (Intel) > Acked-by: Andy Lutomirski > --- > arch/x86/include/asm/entry-common.h | 11 +++++++++-- > 1 file changed, 9 insertions(+), 2 deletions(-) > > --- a/arch/x86/include/asm/entry-common.h > +++ b/arch/x86/include/asm/entry-common.h > @@ -18,8 +18,16 @@ static __always_inline void arch_check_u > * state, not the interrupt state as imagined by Xen. > */ > unsigned long flags = native_save_fl(); > - WARN_ON_ONCE(flags & (X86_EFLAGS_AC | X86_EFLAGS_DF | > - X86_EFLAGS_NT)); > + unsigned long mask = X86_EFLAGS_DF | X86_EFLAGS_NT; > + > + /* > + * For !SMAP hardware we patch out CLAC on entry. > + */ > + if (boot_cpu_has(X86_FEATURE_SMAP) || > + (IS_ENABLED(CONFIG_64_BIT) && boot_cpu_has(X86_FEATURE_XENPV))) > + mask |= X86_EFLAGS_AC; Is the explicit Xen check necessary? IIRC the Xen hypervisor will filter out the SMAP bit in the cpuid pvop. -- Brian Gerst