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From:   Andy Shevchenko <andy.shevchenko@gmail.com>
Date:   Thu, 3 Sep 2020 14:01:08 +0300
Message-ID: <CAHp75Vd3wjNHdYC_A1EVV+kzN=6SGqP2qQ0Wb6pdZWWt9qMMLw@mail.gmail.com>
Subject: Re: [RESEND PATCH v14 2/2] PCI: hip: Add handling of HiSilicon HIP
 PCIe controller errors
To:     Shiju Jose <shiju.jose@huawei.com>
Cc:     Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
        "linux-acpi@vger.kernel.org" <linux-acpi@vger.kernel.org>,
        "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "rjw@rjwysocki.net" <rjw@rjwysocki.net>,
        "helgaas@kernel.org" <helgaas@kernel.org>,
        "bp@alien8.de" <bp@alien8.de>,
        "james.morse@arm.com" <james.morse@arm.com>,
        "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
        "robh@kernel.org" <robh@kernel.org>,
        "lenb@kernel.org" <lenb@kernel.org>,
        "tony.luck@intel.com" <tony.luck@intel.com>,
        "dan.carpenter@oracle.com" <dan.carpenter@oracle.com>,
        yangyicong <yangyicong@huawei.com>,
        Jonathan Cameron <jonathan.cameron@huawei.com>,
        tanxiaofei <tanxiaofei@huawei.com>,
        Linuxarm <linuxarm@huawei.com>,
        Bjorn Helgaas <bhelgaas@google.com>
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On Thu, Sep 3, 2020 at 1:43 PM Shiju Jose <shiju.jose@huawei.com> wrote:
> >From: Andy Shevchenko [mailto:andriy.shevchenko@linux.intel.com]
> >Sent: 01 September 2020 09:26
> >On Mon, Aug 31, 2020 at 10:26:06PM +0100, Shiju Jose wrote:
> >> From: Yicong Yang <yangyicong@hisilicon.com>

...

> >> +config PCIE_HISI_ERR
> >> +    depends on ACPI_APEI_GHES && (ARM64 || COMPILE_TEST)
> >
> >> +    depends on ACPI
> >
> >Isn't this implied by
> >       drivers/acpi/Kconfig:45:if ACPI
> >?
>
> This can be removed as  ACPI_APEI_GHES depends on ACPI.
>
> Do you have any other comments on this patch?

Nope. The rest is fine to me.

> >> +    bool "HiSilicon HIP PCIe controller error handling driver"
> >> +    help
> >> +      Say Y here if you want error handling support
> >> +      for the PCIe controller's errors on HiSilicon HIP SoCs

-- 
With Best Regards,
Andy Shevchenko